EUV (extreme ultraviolet) lithography has recently begun to be applied to semiconductor mass production, and it is expected that more layers will be applied in the future. In particular, the adoption of EUV is a great advantage in that the number of masks required for ArF immersion lithography can be reduced, which can reduce not only the cost but also the risk of EPE (edge placement error) due to superposition. However, the pattern defects of EUV lithography is still issue, and its high resolution performance has not been fully exploited. In order to further pattern shrink of semiconductors in the future, a major issue is how to reduce these defects.
In this report, we introduce the latest approach for mitigation the defects of EUV lithography patterns. The defects are confirmed not only ADI (after development inspection) but also AEI (after etch inspection).