Over the past few years, patterning edge placement error (EPE), which combines information on variability of pattern sizes and placement between adjacent device layers, has been established as the key metric for patterning budget generation and holistic patterning control. More recently, the emergence of high-throughput SEM tools that provide inspection and large-volume CD metrology capabilities has enabled unprecedented statistical analysis of on-product pattern variability.
In the current paper we address edge placement budget generation as well as potential for improved patterning control for an HVM use case at the 28nm litho node. Edge placement and possible related defect mechanisms arise most critically at the contact layer, where contact hole patterning and EPE, with respect to both underlying gate and active layers need to be well controlled. At the 28nm node and for automotive applications, variability control within 5-sigma, i.e. to failure rates below 1 ppm, is generally required to ensure device reliability.
To support generation of an EPE budget by wafer data that captures inter and intra-field components, including local stochastic variations, we use a high-throughput, large field-of-view SEM tool from Hermes Microvision, at all three process layers of interest, as well as YieldStar metrology for overlay characterization. The large volume of data being made available -tens of millions of individual CD measurements- allows mapping out the low-probability ends of variability distributions and detecting non-Gaussian ‘fat tails’ indicative of defect rates that would be underestimated by 3-sigma estimates. Data analysis includes decomposing the total pattern variations into sources of variability, such as global CDU, mask variations and local stochastics. In addition to established CD metrology, we apply novel SEM image based analysis of repetitive patterns in SRAM arrays to generate 2-dimensional process variability bands, including estimates of pattern placement. This approach allows to investigate in detail the probabilistic interaction between active, gate and contact layers.
Spacer-assisted pitch multiplication is a patterning technique that is used on many different critical layers for memory and logic devices. Pitch walk can occur when the spacer process, a combination of lithography, deposition and etch processes, produce a repeating, non-uniform grating of space / line CDs. It has been shown that for spacer-assisted double patterning (SADP), where the lithography pitch is doubled, pitch walk can be reduced by controlling the exposure dose such that the uniformity of the final SADP spaces defined by the core resist mandrel (S1) is balanced with the final SADP space defined by the distance between adjacent SADP lines (S2). For higher pitch multiplications, starting with spacer-assisted quadruple patterning (SAQP) reducing systematic pitch walk with exposure dose becomes more complex.
Co-optimization of the lithography and etch processing is expected to be required to achieve the best pitch walk control. Previous work has shown that improving the across wafer CD uniformity of the line patterns after core etch has limited impact on the space CD uniformity after the SADP process, whereas the CD uniformity of the spaces after SAQP did show some dependence. There are additional space populations created by an SAQP process. The variation of these different populations, along with the spacer deposited line populations, is the root cause of the non-uniform grating that results in pitch walk. The complex interactions of the lithography and etch processes’ impact on the CD and profile need to be understood to produce the optimal performance.
Pitch walk is a component of the overall Edge Placement Error (EPE) budget. With current nodes using SAQP for multiple device layers and future nodes expected to continue to implement this patterning technique, minimization of pitch walk variability is an important part of overall patterning optimizations. In this work, we will show how cooptimized exposure dose and etch processes for SAQP patterning can improve pitch walk performance. We will provide a target exposure dose metric for a 32nm pitch SAQP grating. The methodology for achieving the best pitch walk performance by combination of etch process optimization with dose correction will also be shown.
Today’s CD-SEM metrology is challenged when it comes to measuring complex features found in patterning hotspots (like tip to tip, tip to side, necking and bridging). Metrology analysis tools allow us to extract SEM contours of a feature and convert them into a GDS format from which dimensional data can be extracted. While the CD-SEM is being used to take images, the actual measurement and the choice of what needs to be measured is done offline. Most of the time this method is used for OPC model creation but barely for process variability analysis at nominal process conditions. We showed in a previous paper  that it is possible to study lithography to etch transfer behavior of a hotspot using SEM contours. The goal of the current paper is to go extend this methodology to quantify process variability of 2D features using a new tooling to measure contour data.
Given the potential impact of distortions within the Field Of View (FOV) of the SEM, we need a method to quantify and describe them. We will show a method to find the magnitude and directions of the distortions. This description will enable assessment of impact on local distance measurements like edge placement errors (EPE) analysis and contour measurements. Knowing the distortions with sufficient resolution and stability can also enable corrections for this phenomenon. We will show that applying this correction in post processing, we can bring back the absolute measurement error from 1.5 nm to 0.3 nm.
Multi-patterning has been adopted widely in high volume manufacturing as 193 immersion extension, and it becomes realistic solution of nano-order scaling. In fact, it must be key technology on single directional (1D) layout design  for logic devise and it becomes a major option for further scaling technique in SAQP. The requirement for patterning fidelity control is getting savior more and more, stochastic fluctuation as well as LER (Line edge roughness) has to be micro-scopic observation aria.
In our previous work, such atomic order controllability was viable in complemented technique with etching and deposition . Overlay issue form major potion in yield management, therefore, entire solution is needed keenly including alignment accuracy on scanner and detectability on overlay measurement instruments. As EPE (Edge placement error) was defined as the gap between design pattern and contouring of actual pattern edge, pattern registration in single process level must be considerable. The complementary patterning to fabricate 1D layout actually mitigates any process restrictions, however, multiple process step, symbolized as LELE with 193-i, is burden to yield management and affordability. Recent progress of EUV technology is remarkable, and it is major potential solution for such complicated technical issues. EUV has robust resolution limit and it must be definitely strong scaling driver for process simplification. On the other hand, its stochastic variation such like shot noise due to light source power must be resolved with any additional complemented technique.
In this work, we examined the nano-order CD and profile control on EUV resist pattern and would introduce excellent accomplishments.
Proc. SPIE. 10143, Extreme Ultraviolet (EUV) Lithography VIII
KEYWORDS: Lithography, Logic, Optical lithography, Etching, Metals, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Double patterning technology, Critical dimension metrology, Semiconducting wafers, Stochastic processes, System on a chip, Back end of line
The imec N7 (iN7) platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. Its design is based on a 42 nm first-level metal (M1) pitch, and a 32 nm pitch for the subsequent M2 layer. With these pitches, the iN7 node is an ‘aggressive’ full-scaled N7, corresponding to IDM N7, or foundry N5.
Even in a 1D design style, single exposure of the 16 nm half-pitch M2 layer is very challenging for EUV lithography, because of its tight tip-to-tip configurations. Therefore, the industry is considering the hybrid use of ArFi-based SAQP combined with EUV Block as an alternative to EUV single exposure. As a consequence, the EUV Block layer may be one of the first layers to adopt EUV lithography in HVM.
In this paper, we report on the imec iN7 SAQP + Block litho performance and process integration, targeting the M2 patterning for a 7.5 track logic design. The Block layer is exposed on an ASML NXE:3300 EUV-scanner at imec, using optimized illumination conditions and state-of-the-art metal-containing negative tone resist (Inpria). Subsequently, the SAQP and block structures are characterized in a morphological study, assessing pattern fidelity and CD/EPE variability. The work is an experimental feasibility study of EUV insertion, for SAQP + Block M2 patterning on an industry-relevant N5 use-case.
Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone.
To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.
Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.
In the early phases of technology development, designers and process engineers have to converge
toward efficient design rules. Their calculations are based on process assumptions and result in a
design rule based on known process variability capabilities while taking into account enough margin
to be safe not only for yield but especially for reliability. Unfortunately, even if designs tend to be
regular, efficient design densities are still requiring aggressive configurations from which it is
difficult to estimate dimension variabilities.
Indeed, for a process engineer it is rather straightforward to estimate or even measure simple one-dimensional
features (arrays of Lines & Spaces at various CD and pitches), but it starts to be less
obvious for complex multidimensional features. After a context description related to the process
assumptions, we will outline the work flow which is under evaluation to enable robust metrology of
2 dimensional complex features.
Enabling new metrology possibilities reveals that process hotspots are showing complex behavior
from lithography to etch pattern transfer.
In this work we studied the interaction of lithography variability and etching for a mature 28 nm
CMOS process. To study this interaction we used a test feature that has been found very sensitive to
lithography process variations. This so-called “golden” hotspot shows edge-to-edge geometries from
88nm to 150nm, thus comprising all the through pitch physics in the lithography pattern transfer [1,
2]. It consists of three trenches. From previous work it was known that through trench there is a
systematic variation in best focus due to the Mask 3D effects. At a given chosen focus, there is a
distinct difference in profiles for the three trenches that will lead to pattern displacement effects
during the etch transfer.
CD and line shape control face tougher technology requirements as the drive towards feature size reduction continues down to the 70nm regime. This poses new challenges not only for the lithography process, but also the metrology tool used to qualify the process. Smaller CDs mean smaller tolerances which puts a premium on the ability of metrology to precisely measure these dimensions. Also the trend towards more sampling and entire wafer uniformity mapping to increase yields makes sampling time a consideration. In this paper, we discuss Nanometrics’ Optical CD technology and its application towards the qualification of a scanner exposure system at 140nm pitch resolution (70nm line-spaces). This OCD technique uses normal incidence polarized reflectometry and a form of the Rigorous Coupled-Wave Analysis (RCWA) to do real-time regression. It is a fast and non-destructive method of measuring grating structures which provides complete interfield and intrafield spatially distributed profiles for all fitted OCD parameters. Analysis of spatially distributed data is critical in separating the sources of error that contribute to scanner qualification as a complete litho system
Wafers with 70nm dense (L/S=1:1) horizontal and vertical lines of resist on BARC were measured for this study. The fields on these wafers were exposed under various defocus conditions, producing small to large changes in the grating profiles. OCD measurements show good sensitivity to all fitted parameters; CD, CD profiles and film thickness. The focus fingerprint is clearly identified in a wafer uniformity map, amid other inter-field and intra-field contributions.
Dynamic repeatability and total test reproducibility metrics are introduced and discussed to quantify the reliability and resolution of the OCD to measure these lines.
Scatterometry was selected as CD metrology for the 65nm CDU system qualification. Because of the dominant reticle residuals component in the 65nm CD budget for dense lines, significant improvements in reticle CD metrology were required. SEM is an option but requires extensive measurements due to the scatterometry grating modules. Therefore a new technique was developed and called SERUM (Spot sensor Enabled Reticle Uniformity Measurements). It uses the on board exposure system metrology sensors to measure transmission that is converted to reticle CD. It has the advantage that an entire reticle is measured within two minutes with good repeatability. The reticle fingerprints correlate well to the SEM measurements. With the improvements in reticle CD metrology offered by SEM and SERUM the reticle residuals component no longer dominates the 65nm budget for CDU system qualification.
Evaluations of CD-metrology tools usually focus on resolution, repeatability and accuracy. These are traditional metrics which relate to the capability to measure a local line width. These metrics do not cover the capability to map the CD fingerprint (uniformity map) of the wafer and scanner field, which are essential for sub-100nm lithography process control. In this study, CD-uniformity wafers of state-of-the-art step-and-scan systems were measured with different metrology tools. Analysis of the results revealed a random contribution that could not be attributed to the exposure tool or to the repeatability of the metrology tool. A test and analysis method was developed to separate out this random contribution from the test results. The level of this random CD variation, called the Total Test Repeatability (TTR), is proposed here as a new metric to compare CD-metrology tools in their capability to generate CD uniformity maps. The method was applied to study CD-SEM, Electrical Line width Measurements and CD-scatterometry. In general, the TTR appears to be much larger than the metrology tool repeatability. As such it is an important figure of merit for CD metrology tools used to reveal fingerprints of reticles, exposure tools or processing tools. The TTR is dependent on the metrology tool, measurement algorithm, but also on materials and processing flow and conditions. Some root causes have been identified, such as the wafer resistivity properties for ELM or line width roughness that appears as CD variation in CD-SEM tools. Modifications can be made in the metrology strategy to suppress the TTR and reveal more reliable CD-uniformity fingerprints.
Minimising Across Retical Line width Variation is a continuous challenge for each resolution node. Having tight critical dimension (CD) uniformity for a large variety of pitches is even more challenging. The causes of the reticle errors originate mainly from writing reticles at the edge of the write-tool's capabilities, and from manufacturing at the edge of etching and processing capabilities. These various reticle errors will subsequently lead to non-uniformity effects on wafer level. The reticle errors can be compensated for using technologies similar to those used to correct for optical proximity effects at wafer level. The errors can be small effects in the nanometer range like write noise or larger effects of 10 nm to 100 nm on reticle level from etching. Many effects that we see on reticle will be made visible on the wafer after exposure on a Step & Scan system. To visualise system performance one can use specific techniques such as selection of lines that are on target. In addition, with extensive measurement these reticle errors can be subtracted and thus removed from the final wafer result. For the investigation use is made of a reticle, which has a variation of 35 pitches for four line widths of 100 nm, 130 nm, 150 nm, and 170 nm at 1X. The reticle underwent extensive measurements, and its characteristics are described from these measurements. In addition, some wafer results are shown.
We report here on initial results for the characterization and modeling of 100 nm lithography features based on normal incidence spectroscopic ellipsometry and polarized reflectometry. In this work, a set of wafers was exposed as focus-exposure and separate focus or exposure matrices to create resists patterns with extremely small variations in CD and pattern shape. These variations were generated along scan, within slit and across full wafer. Optical CD scatterometry was used to extract critical feature parameters such as complete shape and associated linear dimensions. Extracted pattern parameters were compared to FIB sections and used to predict lithography process latitudes. We explore effects of using multi normal incidence ellipsometric signals with various profile models to increase accuracy of extracted lithography parameters. We propose a metric for identifying effects of scan-dynamic does and focus variations upon slit-intrafield and scan- intrafield CD errors. This has been tested over ranges of defocus and exposure that are larger than typical FE latitudes of 100 nm features. As a result of spectroscopic scatterometry calculations of pattern shape, we identified pattern shape variations caused by dose and defocus that are clearly coupled to changes in feature size. These could be used for unique determination of dose-focus deviations using scatterometry-extracted information from measurements of a grating structure.
The objective of the Reticle Error Correction (REC) is to determine the exposure tool fingerprint in the Across Chip Linewidth Variation (ACLV). Extensive reticle and wafer measurements indicate hidden reticle issues contributing to ACLV. Some of these obscure reticle issues originate from the way the mask is produced, e.g. due to mask processing and mask writer equipment. Mask processing is traditionally focused upon as the largest cause for ACLV, but on high quality masks, mask writer properties can appear. In order to take these additional properties into account, an extended REC model is required using information from the "nearest neighbors". If not all the required reticle properties are measured and used, either by choice or by tool inability, then a reticle fingerprint also (partially) dominates the exposure tool fingerprint. The quality of the reticle measurements determines how well the exposure tool fingerprint can be revealed. REC is used to separate reticle and exposure tool contributions from ACLV. The methods that are used, and the results that are obtained, serve as a guide in showing where improvements can be made in mask making, mask metrology and exposure tools.