193nm immersion lithography is the most promising lithography candidate for 45nm node technology and beyond. However, immersion specific issue, such as the immersion specific defect and the leaching of resists compound into immersion fluid, still exists without any effective countermeasure. To realize a productive 193nm immersion lithography process, we have to develop a cost effective material that might be immersion dedicated resist. In this paper, we investigated the leaching with different polymer protective agents and hydrophobicity. It was found that the leaching amount was strongly related to the activation energy of the protective agent and hydrophobicity of the polymer. Higher activation energy of protective agents and higher hydrophobicity of polymer showed less amount of leaching. In this paper, newly developed developable type topcoat TILC<sup>TM</sup>-031 demonstrated the excellent ability of immersion defect prevention.
193nm immersion lithography is the most promising lithographic technology for the semiconductor device manufacturing of 65nm node and below. The advantage of 193nm immersion lithography is the possibility of wider depth of focus (DOF) and higher resolution through the hyper NA lens design greater than 1.0<sup>(1-3)</sup>. In this paper, we investigated the topcoat material film characteristics and evaluated its performance to determine the chemical properties needed for a practical level. The stage scan speed capability evaluation, which is one of the best available method to test the suppression or generation of small water droplet remains on the topcoat film at high-speed stage scan during immersion exposure, was used. And finally we investigated the defectivity of topcoat process utilizing the Nikon EET. The static and dynamic contact angles of water droplet were investigated to characterize the topcoat material. The tilting sliding and receding angle, the contact angle of water droplet at the dynamic state, were important parameters to characterize the topcoat materials and have good correlation to wafer stage scan speed capability and immersion defect count reduction.