Downscaling between various video sizes is an important field in transcoding, especially in the era of communication and consumer electronics. Architectures are proposed to offer the best strategy in downscaling. We combine an intra refresh mechanism with a partial encode architecture. A new intra refresh decision mechanism is then proposed based on visual quality constraint. Not only does the work improve transcoded video quality, but overall complexity is also kept low. The experiment results show that the proposed work achieves a 0.5 to 2.5-dB advance in quality, compared with intra refresh in the open loop and partial encode architectures.
Deinterlacing is a method to construct a complete image from an interlaced signal. The interlaced signal format is adopted by the Natural Television System Committee (NTSC) based on eye remanence. In previous work, such as traditional edge line averaging (ELA), it used the intra-interpolation to find the minimum difference value without considering the edge and boundary existence. Consequently, it will cause the interpolation value to be blurred at the edge. A novel algorithm, an edge-based correlation adaptive (ECA) method, is proposed. ECA is based on various edge directions to detect the edge. This new intrafield method has better performance on smoothing the edge and stripe. ECA is improved by using a weighted summation of the ELA component to facilitate the interpolation result. We also interpolate the half-pixel value to increase the accuracy for edge detection. We also mention the architecture and very large scale integration (VLSI) implement results.
A revolutionary methodology of SOPC platform-based design environment for multimedia communications will be developed. We embed a softcore processor to perform the image compression in FPGA. Then, we plug-in an Ethernet daughter board in the SOPC development platform system. Afterward, a web surveillance platform system is presented. The web surveillance system consists of three parts: image capture, web server and JPEG compression. In this architecture, user can control the surveillance system by remote. By the IP address configures to Ethernet daughter board, the user can access the surveillance system via browser. When user access the surveillance system, the CMOS sensor
presently capture the remote image. After that, it will feed the captured image with the embedded processor. The embedded processor immediately performs the JPEG compression. Afterward, the user receives the compressed data via Ethernet. To sum up of the above mentioned, the all system will be implemented on APEX20K200E484-2X device.
MPEG Layer III (MP3) audio coding algorithm is a widely used audio coding standard. It involves several
complex coding techniques and is therefore difficult to create an efficient architecture design. The variable length
decoding (VLD) e.g. Huffman decoding, is an important part of MP3, which needs great amount of search and memory
access operations. In this paper a data driven variable length decoding algorithm is presented, which exploits the signal
statistics of variable length codes to reduce power and a two-level table lookup method is presented. The decoder was
designed based on simplicity and low-cost, low power consumption while retaining the high efficiency requirements.
The total power saving is about 67%.
In this paper, the JPEG2000 encoder with fast Embedded Block Coding with Optimized Truncation (EBCOT) algorithm is implemented with Philips TriMedia TM-1300. EBCOT is the most important technology in the latest image coding standard, JPEG2000.Our aim is to use the advantage between fast EBCOT algorithm and DSP. Fast EBCOT algorithm on JPEG2000 can enhance the ability of image and commercial applications. Therefore, the feasibility and cost of implantation is the key issue. The proposed design can be implemented on TM-1300 platform quickly, and the design time and cost can reduce largely. The fast algorithm used on EBCOT context model can reduce the clock cycle to 32%~38% comparing to the original one.