We present a compiler for programming quantum architectures based on the Quantum Random Access Machine
(QRAM) model. The QRAM model consists of a classical subsystem responsible for generating the quantum
operations that are executed on a quantum subsystem. The compiler can also be applied to trade studies
for optimizing the reliability and latency of quantum programs and to determine the required error correction
resources. We use the Bacon-Shor [9, 1, 3] quantum error correcting code as an example quantum program that
can be processed and analyzed by the compiler.
We design and implement a SIMD scheduler that returns the distribution of quantum operations when taking into account
communication and layout constraints. We define the ion-motion path interface for trapped ion quantum computing architectures
and analyze the design constraints involved in assembling the control circuitry necessary to implement this
interface. Finally, we describe an Instruction Set Architecture (ISA) that we can use to optimize and provide a library of
fault-tolerant building blocks for scalable quantum computation.
Irrespective of the underlying technology used to implement a large-scale quantum architecture system, one of the central challenges of accurately modeling the architecture is the ability to map and schedule a quantum application onto a physical grid while taking into account the cost of communication, the classical resources, and the maximum exploitable parallelism. In this paper we introduce and evaluate a physical operations scheduler for arbitrary quantum circuits. Our scheduler accepts a description of a circuit together with a description of a specific physical layout and outputs a sequence of operations that expose the required communication and available parallelism in the circuit. The output of the scheduler is a quantum assembly language file that can directly be simulated on a set of available tools.
Exploiting recent advances in quantum trapped-ion technologies, we propose a scalable, fault-tolerant quantum computing architecture
that overcomes the fundamental challenges of building a full-scale quantum computer and leaves the fabrication a daunting but primarily
an engineering concern. Using a hierarchical array-based design and a quantum teleportation communication protocol, we are able to
overcome the primary scalability challenges of reliability, communication, and quantum resource distribution.
In particular, we present a reconfigurable quantum circuit substrate, or "quantum FPGA'' (qFPGA) which allows efficient implementation of universal quantum gates and error correction. We
use this qFPGA as a basic building block for an array structure that scalably provides communication channels and quantum resource
distribution. We exploit a hierarchical combination of ballistic transport of data ions and quantum teleportation to reduce the cost
of reliable communication from exponential to polynomial in distance.
By using a set of simulation tools we are able to evaluate a hypothetical design of a future general purpose quantum computer and describe the execution of a fault-tolerant Toffoli gate construction. Without considering classical control constraints and assuming best-possible ion-trap parameters our computer consists of
level 2 encoded qubits with the Steane \ecc code tightly connected by the teleportation interconnect, and capable of executing a fault-tolerant Toffoli gate in roughly 2.3 seconds. This translates to factoring a 128-bit number in slightly over 40
hours in circuits dominated by Toffoli gates.