This presentation introduces the technology and capabilities of the current ULTRA mask writer by Heidelberg Instruments and explains more in detail the possibilities to enhance the performance by introducing software-based optimizations with the MASKER and BEAMER software tools introduced by Genisys GmbH. We will discuss the results for CD linearity and CD uniformity accomplished by ULTRA, the feature fidelity correction and will also look at plans for further developments.
We introduce a complete methodology for process window optimization in proximity mask aligner lithography. The
commercially available lithography simulation software LAB from GenISys GmbH was used for simulation of light
propagation and 3D resist development. The methodology was tested for the practical example of lines and spaces, 5 micron
half-pitch, printed in a 1 micron thick layer of AZ® 1512HS1 positive photoresist on a silicon wafer. A SUSS MicroTec
MA8 mask aligner, equipped with MO Exposure Optics® was used in simulation and experiment. MO Exposure Optics®
is the latest generation of illumination systems for mask aligners. MO Exposure Optics® provides telecentric illumination
and excellent light uniformity over the full mask field. MO Exposure Optics® allows the lithography engineer to freely
shape the angular spectrum of the illumination light (customized illumination), which is a mandatory requirement for
process window optimization. Three different illumination settings have been tested for 0 to 100 micron proximity gap.
The results obtained prove, that the introduced process window methodology is a major step forward to obtain more robust
processes in mask aligner lithography. The most remarkable outcome of the presented study is that a smaller exposure gap
does not automatically lead to better print results in proximity lithography - what the “good instinct” of a lithographer
would expect. With more than 5'000 mask aligners installed in research and industry worldwide, the proposed process
window methodology might have significant impact on yield improvement and cost saving in industry.
Since multi electron beam exposure has become a serious contender for next generation mask making, proximity- and
process effect corrections (PEC) need to be adapted to this technology. With feature sizes in the order of the short-range
blurs (resist and tool), contrast enhancements need to be combined with standard linearity corrections. Different PEC
strategies are reviewed and compared with respect to their suitability for multi-beam exposure. This analysis
recommends a hybrid approach that combines the benefits of shape- and dose PEC and is optimally applicable for multibeam
exposure. Exposure results on the proof-of-concept 50keV electron multi-beam mask exposure tool (eMET POC) and a standard
50 kV vector shaped beam tool (VSB) are shown to verify that the combined PEC with overdose contrast enhancement
covers the whole pattern range from isolated to opaque.
To overcome several drawbacks of the standard pattern copy procedure used to create the repair shape(s) for a particular defect site, we have developed and implemented a layout based pattern copy method (a.k.a. "database pattern copy"). In general, pattern copy derives the repair structure by comparing a high resolution image of the defective area with the same image of a non-defective area. The repair shape is generated as the difference of these two images, and adjusted for processing purposes. As opposed to the conventional pattern copy method, which derives the reference using information taken from the mask under repair, the new method uses reference information from the original mask design file. As a result, it reduces the CD error of the repair, simplifies the repair process work flow, and greatly reduces the potential of operator error. We present the new method along with experimental results taken from programmed defect repair on our MeRiT MGTM production tool.
E-Beam Lithography is still the driving technology for semiconductor manufacturing of critical levels at the 45nm node. Mask costs, yields and representation of the mask on wafer are important factors to consider. Mask-less E-beam lithography is being considered, but major manufacturing is still done by scanner technology. Therefore the same emphasis on modeling applied in the 1990's on the wafer is now being applied to mask technologies to drive down costs, improve yields and to develop viable mask to wafer transfer patterns.
Yield is ultimately connected to process latitude, which is limited by a variety of electron-material interaction issues. As in the optical world, the question is how to maximize the process window considering all the systematic and statistical error sources. Simulation can be used to find out the magnitude of yield limiting effects, and to evaluate the contributing error sources such as PEC file contributions. Film stacks are now becoming an important contributor to statistical error due to technologies such as tri-tone attenuated masks that place a thin layer of chrome over MoSi.
In this paper we will compare the SELID E-beam simulation to cross-sections of line-space and contact patterns. Demonstrations of simulation to real data and the use of simulation to further evaluate process window to enhance the learning mode during development cycles will be presented.
As in optical lithography, E-beam lithography is facing a multitude of issues, both in mask making and in direct write applications. These issues range from pattern printability and design verifications to tool and process optimizations. Simulation can be used to address these issues, however its applicability was limited due to limitations in the usable simulation area. Advances in the mathematical models lead to a significant speedup of the simulation, enabling the simulation of larger areas. This paper will demonstrate the applicability of the new simulator on a few key examples, such as aggressive mask challenges, model to experiment correlations as well as its application to direct write.
In response to next-generation mask requirements, Etec Systems, Inc has developed a complete raster-based patterning solution to meet the production needs of the 130 nm IC device generation as well as those for early 100 nm production. In developing this new MEBES system, we have aimed at versatility, extendability, and compatibility with conventional high-contrast resists and redesigned it form the ground up. This MEBES system incorporates many technological innovations, such as anew 50 kV electron-beam (e-beam) column, a new raster graybeam writing strategy, a new stage, an integrated automated material handling system, on-board diagnostics, and environmental/thermal control. A discussion of architectural details of the new MEBES system designed to meet the tight requirements of 130-100 nm technology nodes is presented. This comprehensive patterning solution offers the best combination of benefits to the user in terms of versatility, overall system throughput, and extendability. Initial throughput and lithographic performance benchmarks are also presented and are very promising in predicting the ability to meet critical dimension uniformity requirements of 10nm or better, as predicted by the ITRS requirements.
This paper describes improvements in column design and writing strategy that, together, enable mask production for the 130 nm technology node. The MEBESR 5500 system employs a new high-dose electron gun and column design. We summarize experiments relating lithographic quality to increased dose and the effects of spot size and input address on lithography. These experiments are performed with ZEP 7000 resist and dry etch. A new graybeam writing strategy, Multipass Gray-II (MPG- II), is described in detail. This strategy creates eight dosed gray levels and provides increased writing throughput (up to 8X, compared to single-pass printing) without loss of lithographic quality. Significantly, critical dimension (CD) uniformity, butting, and other important specifications are improved with MPG-II. Lithographic results and throughput data are reviewed. A consequence of the improvement in CD control and throughput is greater productivity for 180 nm devices.
System architecture choices for an advanced mask writer (100 - 130 nm) have been evaluated. To compare and contrast variably shaped beam vector architecture with raster-based architecture, factors such as beam accelerating voltage and its effects on lithographic performance and system throughput for complex patterns have been studied. The results indicate that while both architectures have strengths and weaknesses, in the final analysis, raster-based systems offer the best combination of benefits to the user in terms of versatility and overall system throughput. Furthermore, other system requirements needed to support the challenges of the next generation mask writers are discussed. An architecture that includes a 50 kV raster graybeam (RGB), based architecture, a new writing strategy, a new stage system, an advanced environmental/thermal control management system, an automated material handling system, and a new resist and process is proposed.
Gray-level printing is an efficient strategy to create small-address patterns on photomasks. This work provides a technical description of the multipass gray (MPG) raster- scan writing technique as implemented on the MEBES 4500S and MEBES 5000 electron-beam pattern generation tools. The differences between single-pass printing (SPP) and MPG are reviewed. The factors that allow increase in throughput and dose with MPG are explained. Aerial image simulations of edge placement and corner rounding verify the MPG model. Multipass writing with offset scan voting, which reduces random and systematic errors, is explained. Because MPG is a gray-level printing technique, the dose distribution across feature edges is necessarily broader than that derived from SPP writing. Simulations and experimental results indicate that, using ZEP 7000 resist and dry etch, edges can be placed without loss of accuracy, despite the width of this 'gray' profile. The spot size necessary to obtain optimal critical dimension quality is also determined by simulation and empirically. The lithographic quality of MPG writing/processing is confirmed by composite metrology test that sample the whole quality area of the mask. We conclude that MPG is a viable technique for writing advanced masks.
Etec Systems, Inc. has developed a new e-beam mask lithography system, the MEBES 4500S, featuring a higher productivity writing strategy called multipass gray and a number of mechanical and electrical improvements. This new system, based on the proven technologies introduced in the MEBES 4500 system, provides improved throughput and accuracy. The MEBES 4500S system with multipass gray supports smaller mask design addresses needed for high resolution masks, while providing higher dose for high contrast processes with low sensitivity and improved CD linearity. Improved print performance is achieved by the introduction of several system design changes that work in conjunction with the multipass gray writing mode. These changes include improved column deflection system temperature control, enhanced TFE current control, improved work chamber thermal management, and improved stage drive vibration damping. Details of these features are presented along with first performance data for the new system.
Both e-beam and optical proximity effects are still a major barrier in the transfer of an ULSI design from the CAD station to the printed result on wafer. Optical proximity effect correction (OPC) is shown to be a strong tool to improve the printing latitudes for i-line lithography of 0.35 micrometers feature sizes and below, but leads to fractal geometries around 0.1 micrometers (corresponding to 0.5 micrometers on a 5x reticle). This quantum leap in required minimum linewidth on the mask may urge mask makers to apply e-beam proximity effect correction (PEC), even more than a decrease in the reticle magnification from 5x to 4x (and further) would. For raster scan e-beams, which are typically used in mask making, correction by dose variation is not practical. Hence, PEC for these systems must be tackled by modifying the geometry of the design, in a way similar to OPC techniques. Both corrections must compromise between the accuracy achieved, which is dominated by the selected (correction and exposure) grid size, and the resulting throughput loss, caused by the use of a smaller grid size. Sigma-C now introduces a new algorithm, which enables the proximity effect correction by shape variation. It is included into CAPROX and supports hierarchy in the same manner as the other postprocessing operations. The exposure of the shape corrected pattern on a raster scan machine requires only one beam pass, whereas dose variation would require one pass for each dose. Exposures were made at IMEC and at Compugraphics. The first results on Leica EBMF10.5 and MEBES III are promising. The pure shape correction increases the line width uniformity and opens the process window for critical dimensions below 1 micrometers . Performance measurements show that the 64 Mb DRAM is a job of a few hours.
The proximity effect in e-beam lithography is well known and many solutions exist to correct it. But none of them are able to cope with the amount of data in today's large scale memories. In a conventional approach, the 64 Mb DRAM would lead to 10 Gigabytes of flat data and weeks of processing time, for example. Recently, Sigma-C achieved a breakthrough in handling USLIs by developing a generic algorithm for many different hierarchical processes. It solves throughput problems for operations like overlap removal (OLR); the e-beam (EPC) and optical proximity correction (OPC) which, at first glance, are inaccessible to hierarchical processing. Hierarchical algorithms take advantage of the growing symmetry of a layout with the number of designed shapes. Even after all processing steps a ULSI device will have hierarchy, not necessarily the same as on input, but yet enough to significantly decrease processing times. Hierarchical processing is a general outline which can be used for many different applications. Most parts of this algorithmic scheme are identical, only one part must be adapted for each application. This paper shows the general outline of hierarchical processing and the solution of the algorithmic steps specific to the hierarchical e-beam proximity correction. Subsequently, the application on a variety of critical layers of the 64 and 256 Mb DRAM is demonstrated using a workstation. Corrected and uncorrected exposures are compared by SEM pictures and line width measurements. The correction not only opens the process window, it turns out to be an enabling technique for critical layers.