Ushasree Katakamsetty
SMTS at GLOBALFOUNDRIES Singapore
SPIE Involvement:
Author
Area of Expertise:
Place and Route , Design for Manufacturing (DFM) , Fill , Static Timing Analysis , CMP , DRC
Profile Summary

Broad experience in various aspects of physical place & route, low power, design rule development, physical verification, DFM, test chip design and semiconductor process development

Specialties:
. Physical Place & Route with low power features, RTL-GDS flow
. Hands on experience on all major EDA tools used for VLSI chip design
. PEX, Static timing analysis and Physical verification DRC & LVS
. DFM Rule based and Model based up to the advanced process nodes of 14nm
. Testchip design, layout, testing methodology, metrology data collection and analysis
. CMP modeling, Fill synthesis, Manufacturability weak points analysis and fixing
Publications (9)

PROCEEDINGS ARTICLE | March 28, 2017
Proc. SPIE. 10148, Design-Process-Technology Co-optimization for Manufacturability XI
KEYWORDS: Oxides, Metrology, Data modeling, Calibration, Metals, Silicon, Manufacturing, Chemical mechanical planarization, Back end of line, Front end of line

PROCEEDINGS ARTICLE | March 16, 2016
Proc. SPIE. 9781, Design-Process-Technology Co-optimization for Manufacturability X
KEYWORDS: Data modeling, Calibration, Etching, Metals, Copper, Silicon, Manufacturing, Design for manufacturing, Semiconducting wafers, Product engineering, Chemical mechanical planarization, Back end of line, Design for manufacturability

PROCEEDINGS ARTICLE | September 4, 2015
Proc. SPIE. 9661, 31st European Mask and Lithography Conference
KEYWORDS: Lithography, Data modeling, Metals, Finite element methods, Photomasks, Optical proximity correction, Semiconducting wafers, Surface finishing, Resolution enhancement technologies, Chemical mechanical planarization

PROCEEDINGS ARTICLE | March 18, 2015
Proc. SPIE. 9427, Design-Process-Technology Co-optimization for Manufacturability IX
KEYWORDS: Lithography, Metals, Silicon, Manufacturing, Design for manufacturing, Chemical analysis, Nanoimprint lithography, Failure analysis, Chemical mechanical planarization, Design for manufacturability

PROCEEDINGS ARTICLE | March 18, 2015
Proc. SPIE. 9427, Design-Process-Technology Co-optimization for Manufacturability IX
KEYWORDS: Polishing, Metrology, Data modeling, Visualization, Calibration, Metals, Manufacturing, Semiconducting wafers, Surface finishing, Chemical mechanical planarization

PROCEEDINGS ARTICLE | March 28, 2014
Proc. SPIE. 9053, Design-Process-Technology Co-optimization for Manufacturability VIII
KEYWORDS: Lithography, Scanners, Copper, Manufacturing, Finite element methods, Design for manufacturing, Semiconducting wafers, Surface finishing, Chemical mechanical planarization, Design for manufacturability

Showing 5 of 9 publications
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