Dr. Uwe Paul Schroeder Profile

Dr. Uwe Paul Schroeder

Manager at ASML

SPIE Involvement:

Author

Publications (36)

Proceedings Article | 22 April 2024 Poster + Paper

Poster + Paper

Advanced pattern selection and coverage check for computational lithography

Keonwoo Bae, Taekyum Kim, Sanghwa Lee, Bongkeun Kim, Seongtae Jeong, Jenny Tang, Qian Zhao, Yiqiong Zhao, Chang-Il Choi, Jiao Liang, Uwe Paul Schroeder, Mark Simmons

Proceedings Volume 12957, 129571M (2024) https://doi.org/10.1117/12.3009845

KEYWORDS: Calibration, Optical proximity correction, Extreme ultraviolet, Data modeling, Education and training, Performance modeling, Advanced patterning, Metrology, Machine learning, Databases

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Proceedings Article | 28 April 2023 Presentation + Paper

Presentation + Paper

Design for manufacturability (DFM) physical verification using machine learning

Lynn T. Wang, Klaus-Peter Johnsen, Ivan Tanev, Fadi Batarseh, Chang Su, Pouya Rezaeifakhr, Uwe Paul Schroeder

Proceedings Volume 12495, 124951G (2023) https://doi.org/10.1117/12.2658646

KEYWORDS: Data modeling, Machine learning, Neural networks, Design and modelling, Design for manufacturing, Principal component analysis, Correlation coefficients, Singular value decomposition, Mathematical optimization, Lithography

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Proceedings Article | 28 April 2023 Presentation + Paper

Presentation + Paper

Design for manufacturability (DFM) in-design fixing for improving manufacturability aware scoring (MAS)

Ariel De Jesus Reyes Ruiz, Lynn T. Wang, Fadi Batarseh, Uwe Paul Schroeder

Proceedings Volume 12495, 124950V (2023) https://doi.org/10.1117/12.2659397

KEYWORDS: Design and modelling, Design for manufacturing, Design rules, Manufacturing, Library classification systems, Image classification, Design for manufacturability, Yield improvement, Target detection, Profiling

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Proceedings Article | 28 April 2023 Presentation + Paper

Presentation + Paper

Machine learning architecture evaluation for fast and accurate weak point detection

Yi Lee, Uwe Paul Schroeder, Pouya Rezaeifakhr, Lynn Wang, David Villarreal

Proceedings Volume 12495, 1249519 (2023) https://doi.org/10.1117/12.2657156

KEYWORDS: Design and modelling, Design for manufacturing, Design rules, Machine learning, Data modeling, Statistical modeling, Statistical analysis, Chip manufacturing

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Proceedings Article | 26 May 2022 Presentation + Paper

Presentation + Paper

Dynamic pattern match searching flow to enable precise hotspot detection

Fadi Batarseh, Uwe Paul Schroeder, Jeff Nelson, Piyush Pathak, Wei-Long Wang, Ya-Chieh Lai

Proceedings Volume 12052, 120520O (2022) https://doi.org/10.1117/12.2617261

KEYWORDS: Data modeling, Machine learning, Silicon, Feature extraction, Optical proximity correction, Metals, Fuzzy logic, Profiling, Databases, Data processing

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Proceedings Article | 26 May 2022 Presentation + Paper

Presentation + Paper

Retargeting-aware design for manufacturability (DFM) checks using machine learning

Lynn T. Wang, Uwe Paul Schroeder, Punitha Selvam, Fadi Batarseh, Pouya Rezaeifakhr, Ariel de Jesus Reyes, Teodora Nicolae, Ivan Tanev, Sriram Madhavan

Proceedings Volume 12052, 1205211 (2022) https://doi.org/10.1117/12.2614460

KEYWORDS: Design for manufacturing, Machine learning, Feature extraction, Metals, Computer aided design, Data modeling, Manufacturing, Neural networks, Design for manufacturability, Data processing

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Proceedings Article | 26 May 2022 Presentation + Paper

Presentation + Paper

Machine learning architecture evaluation for fast and accurate weak point detection

Suraag Sunil Tellakula, Uwe Paul Schroeder, Janam Bakshi, Punitha Selvam, Fadi Batarseh, Pouya Rezaeifakhr, Sriram Madhavan

Proceedings Volume 12052, 120520K (2022) https://doi.org/10.1117/12.2613828

KEYWORDS: Computational lithography, Immersion lithography, Data modeling, Machine learning, Neurons, Design for manufacturing, Neural networks

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Proceedings Article | 22 February 2021 Presentation + Paper

Presentation + Paper

Pattern similarity profiling using semi-supervised learning algorithm

Fadi Batarseh, Uwe Paul Schroeder, Jeff Nelson, Ya-Chieh Lai, Piyush Pathak, Sriram Madhavan, Philippe Hurat

Proceedings Volume 11614, 1161409 (2021) https://doi.org/10.1117/12.2586112

KEYWORDS: Profiling, Tolerancing, Silicon, Manufacturing, Visualization, Semiconducting wafers, Lithography, Inspection, Design for manufacturability

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Proceedings Article | 22 February 2021 Presentation + Paper

Presentation + Paper

Machine-learning assisted fast critical area analysis

Uwe Paul Schroeder, Janam Bakshi, David Villarreal

Proceedings Volume 11614, 116140V (2021) https://doi.org/10.1117/12.2582844

KEYWORDS: Machine learning, Yield improvement, Shape analysis, Semiconductors, Multilayers, Metals, Design for manufacturing

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Proceedings Article | 22 February 2021 Presentation + Paper

Presentation + Paper

Deep learning-based hotspot prediction of via printability in process window corners

Punitha Selvam, Pouya Rezaeifakhr, Uwe Paul Schroeder, Janam Bakshi, Omnia Mohamed, Fadi Batarseh, Sriram Madhavan

Proceedings Volume 11614, 116140X (2021) https://doi.org/10.1117/12.2583662

KEYWORDS: Data processing, Data modeling, Multilayers, Dynamic signature verification, Semiconductors, Profiling, Machine learning, Design for manufacturing, Convolutional neural networks

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With more advanced semiconductor technologies, identifying process weak points becomes more complex as multiple layers need to be taken into consideration. In recent years, traditional rule based weak point identification has been augmented by pattern matching to pinpoint and fix possible design weak points. Traditional methods of pattern definition are done by profiling the designs for weak points to capture the patterns of interest for applying opportunistic fixes. Patterns are usually handcrafted by taking process information into account, and applying fixes on the design features. Some fail modes have emerged recently that are a result of very complex multi layer interactions. These types of weak points are very difficult to define comprehensively with traditional pattern matching. Recently, deep learning has undergone a rapid development and tools are now available that can learn based on large amounts of process data. We have harnessed this to address the problem of identifying complex weak points with low escape rates. In this paper, we provide a review on a deep learning based weak point detection flow taking retargeting/opc/orc simulations into account as training data. Using the deep learning approach, the process data is abstracted as an encrypted machine learning model, and released to designers as part of the GLOBALFOUNDRIES (GF) DRC+ tool. This tool is shipped with the PDK, and can be used to fix the design, mitigating process weak points. This paper begins with a brief introduction to the deep learning TensorFlow model using Convolutional Neural Network (CNN) widely used for image detection. Then we focus on feature density vector (DSV) generation to extract the layout parameters and labels used for training the model. Experimental analysis is also provided to compare recall and precision metrics of POR and ML methods in detecting the weak point on a via layer at process window conditions. Our case study shows that the ML flow improves the pattern capture rate by 34% over standard hotspot detection methods. As a conclusion, we will also brief on our future work leveraging the ML flow for other weak point detections.

Proceedings Article | 22 February 2021 Presentation + Paper

Presentation + Paper

Electrical design-for-manufacturability (DFM) checks for reducing layout-induced circuit variability of analog designs

Lynn Wang, Michael Simcoe, Vikas Mehrotra, Rais Huda, Zhao Chuan Lee, Thomas McKay, Uwe Paul Schroeder, Sriram Madhavan

Proceedings Volume 11614, 116140L (2021) https://doi.org/10.1117/12.2583839

KEYWORDS: Analog electronics, Design for manufacturing, Metals, Resistance, Capacitance, Databases, Back end of line, Tolerancing, Mirrors, Manufacturing

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Proceedings Article | 23 March 2020 Presentation + Paper

Presentation + Paper

Dynamic pattern matching flow to enable low escape rate weak point detection

Uwe Paul Schroeder, Janam Bakshi, Ahmed Mounir Elsemary, Fadi Batarseh

Proceedings Volume 11328, 113280D (2020) https://doi.org/10.1117/12.2551739

KEYWORDS: Databases, Image classification, Lithography, Metals, Printing, Digital electronics, Optical proximity correction, Machine learning

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Proceedings Article | 23 March 2020 Presentation + Paper

Presentation + Paper

Co-optimizing DFM enhancements and their impact on layout-induced circuit performance for analog designs

Lynn Wang, Michael Simcoe, Vikas Mehrotra, Gail Katzman, Rais Huda, Zhao Chuan Lee, Janam Bakshi, Ahmed Abdulghany, Uwe Paul Schroeder, Sriram Madhavan

Proceedings Volume 11328, 113280M (2020) https://doi.org/10.1117/12.2551945

KEYWORDS: Design for manufacturing, Analog electronics, Databases, Device simulation, Metals, Manufacturing, Transistors, Mirrors, Design for manufacturability, Amplifiers

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Proceedings Article | 20 March 2019 Presentation + Paper

Presentation + Paper

Optimizing DFM scores by using a genetic evolution algorithm

Uwe Paul Schroeder, Ahmed Shalabi, Janam Bakshi, Mohamed Ismail, Ahmed Mounir Elsemary

Proceedings Volume 10962, 109620J (2019) https://doi.org/10.1117/12.2515094

KEYWORDS: Evolutionary optimization, Design for manufacturing, Evolutionary algorithms, Genetic algorithms, Machine learning, Optical lithography, Logic

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Proceedings Article | 20 March 2019 Presentation + Paper

Presentation + Paper

Design for manufacturability for analog, radio frequency, and millimeter wave designs

Lynn Wang, Gail Katzman, Yongfu Li, Vikas Mehrotra, Janam Bakshi, Ahmed Abdulghany, Michael Simcoe, Rais Huda, Zhao Chuan Lee, Don Blackwell, Thomas Hermann, Uwe Paul Schroeder, Thomas McKay, Sriram Madhavan

Proceedings Volume 10962, 109620G (2019) https://doi.org/10.1117/12.2514769

KEYWORDS: Design for manufacturing, Analog electronics, Manufacturing, Chemical mechanical planarization, Design for manufacturability, Metals, Extremely high frequency, Yield improvement, Digital electronics, Transceivers

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Proceedings Article | 4 April 2018 Presentation + Paper

Presentation + Paper

Litho friendly via insertion with in-design auto-fix flow using machine learning

Ahmed Mounir Elsemary, Moutaz Fakhry, Janam Bakshi, Nishant Shah, Mohamed Ismail, Fadi Batarseh, Uwe Paul Schroeder, Ahmed Mohyeldin, Jason Cain

Proceedings Volume 10588, 105880F (2018) https://doi.org/10.1117/12.2297499

KEYWORDS: Lithography, Metals, Optical lithography, Manufacturing, Machine learning, Image classification, Design for manufacturing, Library classification systems, Pattern recognition

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Proceedings Article | 3 April 2017 Presentation + Paper

Presentation + Paper

Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs

Ahmed Mohyeldin, Uwe Paul Schroeder, Ramya Srinivasan, Haritez Narisetty, Shobhit Malik, Sriram Madhavan

Proceedings Volume 10148, 101480N (2017) https://doi.org/10.1117/12.2261588

KEYWORDS: Capacitance, Resistance, Metals, Design for manufacturing, Double patterning technology, Databases, Design for manufacturability, Manufacturing, Yield improvement, Photomasks

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In nano-meter scale Integrated Circuits, via fails due to random defects is a well-known yield detractor, and via redundancy insertion is a common method to help enhance semiconductors yield. For the case of Self Aligned Double Patterning (SADP), which might require unidirectional design layers as in the case of some advanced technology nodes, the conventional methods of inserting redundant vias don’t work any longer. This is because adding redundant vias conventionally requires adding metal shapes in the non-preferred direction, which will violate the SADP design constraints in that case. Therefore, such metal layers fabricated using unidirectional SADP require an alternative method for providing the needed redundancy.

This paper proposes a post-layout Design for Manufacturability (DFM) redundancy insertion method tailored for the design requirements introduced by unidirectional metal layers. The proposed method adds redundant wires in the preferred direction - after searching for nearby vacant routing tracks - in order to provide redundant paths for electrical signals. This method opportunistically adds robustness against failures due to silicon defects without impacting area or incurring new design rule violations. Implementation details of this redundancy insertion method will be explained in this paper.

One known challenge with similar DFM layout fixing methods is the possible introduction of undesired electrical impact, causing other unintentional failures in design functionality. In this paper, a study is presented to quantify the electrical impacts of such redundancy insertion scheme and to examine if that electrical impact can be tolerated. The paper will show results to evaluate DFM insertion rates and corresponding electrical impact for a given design utilization and maximum inserted wire length. Parasitic extraction and static timing analysis results will be presented. A typical digital design implemented using GLOBALFOUNDRIES 7nm technology is used for demonstration.

The provided results can help evaluate such extensive DFM insertion method from an electrical standpoint. Furthermore, the results could provide guidance on how to implement the proposed method of adding electrical redundancy such that intolerable electrical impacts could be avoided.

Proceedings Article | 30 March 2017 Presentation + Paper

Presentation + Paper

Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for sub-20nm metal routing

Lynn T. - Wang, Uwe Paul Schroeder, Sriram Madhavan

Proceedings Volume 10148, 1014804 (2017) https://doi.org/10.1117/12.2258061

KEYWORDS: Metals, Photomasks, Lithography, Manufacturing, Double patterning technology, Design for manufacturing, Design for manufacturability, Capacitance, Printing, Computer simulations, Computer aided design, Optical lithography

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Proceedings Article | 18 March 2016 Paper

Paper

EUV and optical lithographic pattern shift at the 5nm node

Erik Hosler, Sathish Thiruvengadam, Jason Cantone, Deniz Civay, Uwe Schroeder

Proceedings Volume 9776, 977616 (2016) https://doi.org/10.1117/12.2217532

KEYWORDS: Extreme ultraviolet, Optical lithography, Photomasks, Monte Carlo methods, Extreme ultraviolet lithography, Lithography, Personal protective equipment, Critical dimension metrology, EUV optics, Transistors

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Proceedings Article | 16 March 2016 Paper

Paper

Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing

Piyush Pathak, Karthik Krishnamoorthy, Wei-Long Wang, Ya-Chieh Lai, Frank Gennari, Shikha Somani, Bob Pack, Uwe Paul Schroeder, Fadi Batarseh, Jaime Bravo, Jason Sweis, Philippe Hurat, Sriram Madhavan

Proceedings Volume 9781, 978109 (2016) https://doi.org/10.1117/12.2220145

KEYWORDS: Design for manufacturing, Mining, Design for manufacturability, Manufacturing, Semiconductor manufacturing, Image classification, Machine learning, Optical proximity correction, Lithography, Semiconductors, Metals, Databases, Charge-coupled devices, Silicon, Data mining, Computer simulations

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Proceedings Article | 16 March 2016 Paper

Paper

Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond

Lynn Wang, Uwe Paul Schroeder, Youngtag Woo, Jia Zeng, Sriram Madhavan, Luigi Capodieci

Proceedings Volume 9781, 97810B (2016) https://doi.org/10.1117/12.2219358

KEYWORDS: Photomasks, Manufacturing, Lithography, Double patterning technology, Metals, Image classification, Library classification systems, Design for manufacturing, Design for manufacturability, Overlay metrology, Optical proximity correction, 193nm lithography

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Proceedings Article | 16 March 2016 Paper

Paper

Hybrid pattern matching based SRAF placement

Ahmed Omran, Andrey Lutich, Uwe Paul Schroeder

Proceedings Volume 9781, 978117 (2016) https://doi.org/10.1117/12.2225830

KEYWORDS: SRAF, Logic, Design for manufacturing, Optical proximity correction, Immersion lithography, Model-based design, Performance modeling, Photomasks, Databases, Lithography, Printing, Photovoltaics, Resolution enhancement technologies, Phase modulation

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Proceedings Article | 16 March 2009 Paper

Paper

Contact mask optimization and SRAF design

Uwe Schroeder, Cyrus Tabery, Bradley Morgenfeld, Hideki Kanai

Proceedings Volume 7274, 727407 (2009) https://doi.org/10.1117/12.814814

KEYWORDS: SRAF, Photomasks, Critical dimension metrology, Printing, Lithography, Fiber optic illuminators, Optical proximity correction, Tolerancing, Data modeling, Optical lithography

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Proceedings Article | 27 March 2007 Paper

Paper

ACLV performance dry vs. immersion on 45-nm ground rules

Uwe Schroeder, Chin-Chin Yap, Chandra Sarma, Alan Thomas

Proceedings Volume 6520, 65204I (2007) https://doi.org/10.1117/12.713113

KEYWORDS: Photomasks, Semiconducting wafers, Critical dimension metrology, Lithography, Scanning electron microscopy, Metrology, Semiconductors, Logic, Scanners, Immersion lithography

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Proceedings Article | 26 March 2007 Paper

Paper

Optimal SRAF placement for process window enhancement in 65-nm/45-nm technology

Chandra Sarma, Klaus Herold, Christoph Noelscher, Paul Schroeder

Proceedings Volume 6520, 65202B (2007) https://doi.org/10.1117/12.711480

KEYWORDS: SRAF, Photomasks, Tolerancing, Semiconducting wafers, Printing, Manufacturing, Lithography, Optical proximity correction, Logic, Standards development

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Proceedings Article | 24 March 2006 Paper

Paper

Comparison of I-line and DUV high-energy implant litho processes

A. Grandpierre, C. Berger, U. Schroeder, R. Schiwon, M. Kubis

Proceedings Volume 6152, 61523V (2006) https://doi.org/10.1117/12.655163

KEYWORDS: Deep ultraviolet, Semiconducting wafers, Ions, Lithography, Photoresist materials, Laser sintering, Photomasks, Reticles, Image processing, Optical proximity correction

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For capacity reasons, it is interesting for us to have the flexibility of switching lithography processes between DUV and I-line steppers. The following discussion concentrates on high energy tilted implants of CMOS technology, critical enough to be worth running on the more expensive DUV equipment. As far as the differences are understood at the level of the printing, as well as the dissimilarities during the following implantation steps, it is possible using the same reticle and with minor target adjustments, to switch between the 2 tools/processes when required. This paper investigates the most important differences between the functionality of a same implant layer making use of the two wavelengths. Taken as high energy implant mask for several successive ion implantations, the resist film considered here is 1.6 pm thick. The taper profiles of I-line and DUV resist are shown after development, and after the successive implantation steps. Both wavelengths provide straight profiles after development, with one main difference: a slight footing for the I-line resist. This can be very well seen on the corresponding top down pictures revealing more tapers for the I-line process than for DUV. The first implantation step following development influences the profiles the most. In fact the profile of the DUV resist changes considerably while the one with I-line resist remains unchanged. That can be explained by the fact that the aliphatic structure of DUV photoresist is less resistant to degradation by ion bombardment as compared to the highly aromatic chemical structure of I-line photoresist. The subsequent implant steps of lower energy do not further influence the tapers, not even in the case of the I-line film. Therefore the biggest shrinkage occurs during the first implantation and all the next ion sequences will see this first deformation without changing it. Finally, simulation show that, an adjustment of the reticle OPC by adding serifs can be beneficial to the I-line layer to diminish corner rounding where the footingkapering can be worse.

Proceedings Article | 15 March 2006 Paper

Paper

Finding the right way: DFM versus area efficiency for 65nm gate layer lithography

Chandra Sarma, Steven Scheer, Klaus Herold, Carlos Fonseca, Alan Thomas, Uwe Schroeder

Proceedings Volume 6154, 61541L (2006) https://doi.org/10.1117/12.656633

KEYWORDS: SRAF, Design for manufacturing, Lithography, Manufacturing, Tolerancing, Atrial fibrillation, Semiconducting wafers, Printing, Lithographic illumination, Optical proximity correction

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Proceedings Article | 12 May 2005 Paper

Paper

The challenge of high-volume 193-nm semiconductor manufacturing

U. Schroder, S. Poelders, T. Fischer, K. Schumacher, A. Kiss, A. Frangen, D. Nees, M. Kubis, G. Erley, B. Janke

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.594628

KEYWORDS: 193nm lithography, Semiconducting wafers, Photoresist materials, Etching, Photomasks, Lithography, Manufacturing, Semiconductor manufacturing, Metrology, Deep ultraviolet

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Proceedings Article | 10 May 2005 Paper

Paper

Critical dimension control on I-line steppers

Roberto Schiwon, Alexandra Grandpierre, Michael Kubis, Uwe Schroder

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.596521

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Reticles, Coating, Process control, Metrology, Photoresist processing, Time metrology, Lithography, Manufacturing

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Proceedings Article | 10 May 2005 Paper

Paper

Standing wave reduction of positive and negative I-line resists

A. Grandpierre, R. Schiwon, F. Finger, U. Schroder

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.596508

KEYWORDS: Lithography, Coating, Bottom antireflective coatings, Reactive ion etching, Doping, Semiconducting wafers, Reticles, Ultraviolet radiation, Temperature metrology, Critical dimension metrology

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Proceedings Article | 28 May 2004 Paper

Paper

Matching OPC and masks on 300-mm lithography tools utilizing variable illumination settings

Katrin Palitzsch, Michael Kubis, Uwe Schroeder, Karl Schumacher, Andreas Frangen

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.532328

KEYWORDS: Photomasks, Critical dimension metrology, Lithography, Optical proximity correction, Lithographic illumination, Semiconducting wafers, Etching, Reticles, Scanners, Monochromatic aberrations

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CD control is crucial to maximize product yields on 300mm wafers. This is particularly true for DRAM frontend lithography layers, like gate level, and deep trench (capacitor) level. In the DRAM process, large areas of the chip are taken up by array structures, which are difficult to structure due to aggressive pitch requirements. Consequently, the lithography process is centered such that the array structures are printed on target. Optical proximity correction is applied to print gate level structures in the periphery circuitry on target. Only slight differences of the different Zernike terms can cause rather large variations of the proximity curves, resulting in a difference of isolated and semi-isolated lines printed on different tools. If the deviations are too large, tool specific OPC is needed. The same is true for deep trench level, where the length to width ratio of elongated contact-like structures is an important parameter to adjust the electrical properties of the chip. Again, masks with specific biases for tools with different Zernikes are needed to optimize product yield. Additionally, mask making contributes to the CD variation of the process. Theoretically, the CD deviation caused by an off-centered mask process can easily eat up the majority of the CD budget of a lithography process. In practice, masks are very often distributed intelligently among production tools, such that lens and mask effects cancel each other. However, only dose adjusting and mask allocation may still result in a high CD variation with large systematical contributions. By adjusting the illumination settings, we have successfully implemented a method to reduce CD variation on our advanced processes. Especially inner and outer sigma for annular illumination, and the numerical aperture, can be optimized to match mask and stepper properties. This process will be shown to overcome slight lens and mask differences effectively. The effects on lithography process windows have to be considered, nonetheless.

Proceedings Article | 24 May 2004 Paper

Paper

Investigation of systematical overlay errors limiting litho process performance of thick implant resists

Alexandra Grandpierre, Roberto Schiwon, Jens Bruch, Christoph Nacke, Uwe Schroeder

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.532334

KEYWORDS: Overlay metrology, Semiconducting wafers, Photoresist processing, Lithography, Error analysis, Diffusion, Manufacturing, Statistical analysis, Etching, Coating

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Proceedings Article | 26 June 2003 Paper

Paper

Exposure field size considerations for yield

Uwe Schroeder, Gerhard Kunkel

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485483

KEYWORDS: Lithography, Critical dimension metrology, Capacitors, Overlay metrology, Reticles, Semiconducting wafers, Semiconductor manufacturing, Tolerancing, Image registration, Deep ultraviolet

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Proceedings Article | 2 June 2003 Paper

Paper

Overlay considerations for 300-mm lithography

Tobias Mono, Uwe Schroeder, Dieter Nees, Katrin Palitzsch, Wolfram Koestler, Jens Bruch, Sirko Kramp, Markus Veldkamp, Ralf Schuster

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.485019

KEYWORDS: Semiconducting wafers, Overlay metrology, Lithography, Manufacturing, Process control, Semiconductors, Optical lithography, Critical dimension metrology, Reticles, Tungsten

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Proceedings Article | 5 July 2000 Paper

Paper

Structure end foreshortening: lithography-driven design limitations

Uwe Schroeder, Dennis Warner

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.388930

KEYWORDS: Photomasks, Lithography, Logic, Optical proximity correction, Metals, Manufacturing, Information operations, Etching, Semiconducting wafers, Neodymium

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Proceedings Article | 5 July 2000 Paper

Paper

OPC for logic and embedded applications: the reverse approach

Uwe Schroeder, Tobias Mono

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.388933

KEYWORDS: Lithography, Optical proximity correction, Logic, Photomasks, Electroluminescence, Information operations, Adaptive optics, Silicon, Lithographic illumination, Phase shifts

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Showing 5 of 36 publications

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