Switching activity of logic gates in a digital system is a deterministic process, depending on both circuit parameters
and input signals. However, the huge number of logic blocks in a digital system makes digital switching a
cognitively stochastic process. Switching activity is the source of the so-called "digital noise", which can be analyzed
using a stochastic approach. For an asynchronous digital network, we can model digital switching currents
as a shot noise process, deriving both its amplitude distribution and its power spectral density. From spectral
distribution of digital currents, we can also calculate the spectral distribution and the power of disturbances
injected into the on-chip power supply lines.
In fully CMOS digital integrated systems, switching activity of logic gates is the source of the so-called "digital
noise". Together with interconnections parasitics, digital switching noise is known to cause "bouncing" effects,
i.e. oscillations of on-chip supply and bias voltages, which can remarkably degrade overall system performance.
Digital switching is a completely deterministic process, depending on both circuit parameters and input signals.
However, the huge number of logic blocks in a digital integrated system makes digital switching a cognitively
stochastic process. Therefore, logic transition activity can be analyzed using a stochastic approach. In this
paper, we model the digital switching current as a stationary shot noise process, and we derive both its amplitude
distribution and its power spectral density.
This paper presents an approach for the analysis and the experimental
evaluation of crosstalk effects due to current pulses drawn from
voltage supplies in mixed analog-digital CMOS integrated circuits. A
realistic model of bonding and package parasitics has been derived
to study digital switching noise injected through bonding
interconnections. Simulations results indicate that disturbances due
to switching currents in digital blocks propagate through the substrate and affect analog voltages, thus degrading circuit performance. Test structures have been integrated into a test chip mounted with different technologies, in order to compare the measurements on test chips. Measurements confirm simulation results.
Chip-on-board mounting technology has better performance with respect to chip-in-package, due to the reduction of parasitic elements.
This paper discusses the use of evolutionary algorithms to design digital circuits. It is shown that evolutionary design can be fully compliant with the existing design methodologies. Moreover, the evolutionary design is capable to perform a better exploration of the design space, and therefore it can find solutions having different features with respect to conventional design. In some cases, evolved circuits can have better performances, or they can be optimized with respect to different parameters. An example on design of a multi-rate digital filter with reduced power consumption is presented and discussed. FPGA implementation demonstrates that evolutionary design can lead to both area and power saving with respect to conventional design.