With continuously shrinking design rules and corresponding low-k1 lithography, defectivity and yield are increasingly dominated by systematic patterning defects. The size of these yield-limiting defects is shrinking along with feature size, making their detection and verification more difficult. We discuss a novel, holistic approach to pattern defect detection and control, which integrates full chip layout analysis and hybrid wafer metrology data to predict wafer locations with highest probability for defect occurrence. We assess the various components of this flow by an experimental study on a 10 nm BEOL process at IMEC, using state-of-the-art negative tone development (NTD) and triple Litho-Etch patterning process.
3D lithography simulations capable of modeling 3D effects in all lithographic processes are becoming critical in OPC
and verification applications as semiconductor feature sizes continue to shrink. These effects include mask topography,
resist profile and wafer topography. In this work we present an efficient computational framework for full-chip 3D
lithography simulations. Since fast modeling of mask topography effects has been studied for many years and is a
relatively mature area, we will only briefly review a full-chip 3D mask model, Tachyon M3D, to highlight the
importance and modeling requirements for accurate prediction of best focus variations among different device features
induced by mask topography. We will focus our discussions on a full-chip 3D resist model, Tachyon R3D, its derivation
and simplification from a full physical resist model. The resulting model form is fully compatible with the existing 2D
resist model with added capabilities for resist profile and top loss prediction. A benchmark against the full physical
model will be presented as well. We will also describe the development of a full-chip 3D wafer topography model,
Tachyon W3D, and the preliminary results against rigorous simulations.
Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage
of non-uniform reflective substrates without bottom anti-reflection coating (BARC).
Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer
topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects
such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without
BARC, e.g., implant layer, as technology node shrinks.
For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated
using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and
resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate
them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if
well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and
they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers
wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full
chip OPC on implant layers.
Traditional scanner matching methods have been based in 1D proximity matching targets
and the use of wafer-based CD metrology to characterize both the initial mismatch as
well as the sensitivity of CDs to scanner tuning knobs.
One such method is implemented in ASML Pattern Matcher, which performs a linear
optimization based on user provided CD sensitivities and pre-match data. The user
provided data usually comes from wafer exposures done at multiple scanner illumination
conditions measured with CD-SEM. In the near future ASML plans to provide the
capability to support YieldStar CD data for Pattern Matcher which will collect CD data
with higher precision and much faster turn-around-time that CD-SEM.
Pattern Matcher has been used successfully in multiple occasions. Results for one such
occasion are shown in Figure 1 which presents the through pitch mismatch behavior of
one ASML XT:1400F with respect to an ASML XT:1400E for a 32nm contact layer.
Proximity matching is a common activity in the wafer fabs1,2,3 for purposes such as
process transfer, capacity expansion, improved scanner yield and fab productivity. The
requirements on matching accuracy also become more and more stringent as CD error
budget shrinks with the feature size as technology advances. Various studies have been
carried out, using scanner knobs including NA, inner sigma, outer sigma, stage tilt,
ellipticity, and dose. In this paper, we present matching results for critical features of a
logic device, between an ASML XT:19x0i scanner and an XT:1700i (reference),
demonstrating the advantage of freeform illuminator pupil as part of the adjustable
knobs to provide additional flexibility. We also present the investigation of a novel
method using lens manipulators for proximity matching, effectively injecting scalar
wavefront to an XT:19x0i to mimic the behavior of the XT:1700i lens.
FlexRay programmable illumination and LithoTuner software is combined in several use cases. The first use case is
optical proximity error (OPE) minimization. Simulation predicts the rms OPE error is reduced by 39% with LithoTuner
and FlexRay, and is confirmed via experiment with a reduction of 33%. For minimizing the OPE error, two types of
illumination tuning was performed, sigma tuning and freeform tuning. The sigma tuning is able to reduce the mean-totarget
critical dimension (CD) error, but the CD error variance is unaffected. Freeform tuning, however, is able to reduce
both the mean-to-target CD and the CD error variance. The second use case is matching two ArF scanners, a XT:1950Hi
with FlexRay to a XT:1700Fi with diffractive optical element (DOE) illumination. With LithoTuner and FlexRay,
simulation predicts the CD error post-matching is reduced by 51%, and experiment was able to achieve a reduction of
Scanner mismatch has become one of the critical issues in high volume memory production. There are several
components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference
between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more
critical in electrical performance and process window.
In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices.
We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer
metrology data and scanner specific parameters are used to build a computational model, and determine the optimal
settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was
used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil
parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and
measured process window changes by applying the matching sub-recipe are also evaluated.
Conventional photomask inspection techniques utilize global sensitivity for all inspected area in the die; SRAF and OPC
features become the sensitivity-limiters for advanced photomasks which can result in reduced sensitivity to defects of
interest (DOI). We describe the implementation of Sensitivity Control Layer (SCL), a novel database inspection
methodology for the KLA-Tencor TerascanHR platform to improve sensitivity and reduce nuisance detections. This
methodology enables inspection at maximum sensitivity in critical die-areas via "layer definition" and reducing
sensitivity to sub-resolution features during inspection which can dramatically improve false-rate. DRAM and FLASH
inspection performance was improved through the use of up to 6-control layers to increase sensitivity in the active area
while reducing false detections by as much as 100X. Post-inspection defect analysis, and improved disposition accuracy
of the SCL-enabled inspections will also benefit cycle time and higher throughput. In all test cases, sensitivity
parameters were increased in the regions of interest over baseline inspections run with typical, production-type
inspection methodologies. SCL inspection-sensitivity management, and layer partitioning of OPC structures, SRAF's,
and other sub-resolution features is discussed in detail.
We have evaluated a unified mask pattern data format named "OASIS.MASK"1 and a unified job deck format
named "MALY"2 for mask tools as the input data formats of the inspection tool using the mask data and the photomask
produced with the 65nm design rule. The data conversion time and the data volume for the inspection data files were
evaluated by comparing with the results for using the native EB data and the native job deck data. The inspection speed
and the defect number of the inspection tool were also evaluated with the actual inspection tool. We have confirmed that
there is no large issue in applying OASIS.MASK and MALY to the input data formats of the inspection tool and they
can become the common intermediate format in our MDP flow. The detail of evaluation results will be mainly
introduced in this paper.
Non-uniformity in reticle CDs can cause yield loss and/or performance degradation during chip manufacturing. As a
result, CD Uniformity (CDU) across a reticle is a very important specification for photomask manufacturing. In addition
the photomask CDU data can be used in a feedback loop to improve and optimize the mask manufacturing process. A
typical application is utilizing CDU data to adjust the mask writer dose and compensate for non-uniformity in the CDs,
resulting in improved quality of subsequent masks.
Mask makers are currently using the CD-SEM for data collection. While the resolution of SEM data ensures its position
as the industry standard, an output map of CDU using the reticle inspection tool has the advantage of denser sampling
over larger areas on the mask. High NA reticle inspection systems scan the entire reticle at high throughput, and are
ideally suited for collecting CDU data on a dense grid.
In this paper, we describe the basic theory of a prototype reticle inspection-based CDU tool, and results on advanced
memory masks. We discuss possible applications of CDU maps for optimizing the mask manufacturing process or in
adjusting scanner dose to improve wafer CD uniformity.
Conventional photomask inspection techniques utilize global sensitivity for all inspected area in the die; SRAF and OPC
features become the sensitivity-limiters, which can result in reduced visibility to defects of interest (DOI). We describe
the implementation of Sensitivity Control Layer (SCL), a novel database inspection methodology for the KLA-Tencor
TerascanHR platform. This methodology enables inspection at maximum sensitivity in critical die-areas via "layer
definition" during job set-up and sensitivity management of the layers during inspection. Memory device inspection
performance was improved through the use of up to six control layers to increase sensitivity in the active area while
reducing nuisance detections by as much as 100X. The corresponding inspection time was reduced by 30%, illustrating
the potential for substantial throughput advantage using SCL. Post-inspection analysis and improved disposition
accuracy of the SCL-enabled inspections will also benefit cycle time and higher throughput. In all test cases, sensitivity
parameters were increased in the regions of interest over baseline inspections run with typical production-use
methodologies. SCL inspection management and application on OPC structures, SRAFs, and MRC violations (slivers)
are discussed in detail.
As the design rule continues to shrink towards 3x nm and below, lithographers are searching for new and
advanced methods of mask lithography such as immersion, double patterning and extreme ultraviolet
lithography (EUVL). EUV lithography is one of the leading candidates for the next generation lithography
technologies after 193 nm immersion and many mask makers and equipment makers have focused on
stabilizing the process. With EUV lithography just around the corner, it is crucial for advanced mask makers
to develop and stabilize EUV mask processes. As a result, an inspection tool is required to monitor and
provide quick feedback to each process step.
The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact the device yield. A technique based on the Phase-Shift Focus Monitor (PSFM) is developed to measure realistic across-wafer focus errors on materials processed in actual production flows. With this technique, we are able to extract detailed across-wafer focus performance at critical pattern levels from the front end of line (FEOL) all the way through the back end of line (BEOL). Typically, more than 8,000 data points are measured across a wafer, and the data are decomposed into an intra-field focus map, which captures the across chip focus variation (ACFV), and an inter-field focus map, which describes the across wafer focus variation (AWFV). ACFV and AWFV are then analyzed to understand various components in the overall focus error, including; across slit lens image field, reticle shape and dynamic scan components, local wafer flatness, wafer processing effect, pattern density, and edge die abnormality. The intra-field ACFV lens component is compared with TI's ScatterLith and ASML's FOCAL techniques. Results are consistent with the predictions based on the on-board lens aberration data. Inter-field AWFV is the most interesting, due to lack of detailed understanding of the process impact on scanner focus and leveling. PSFM data is used to characterize the effect of wafer processing such as etch, deposition, and CMP on across wafer focus control. Comparison and correlation of PSFM focus mapping with the wafer height and residual moving average (MA) maps generated by the scanner's optical leveling sensors shows a good match in general. Process induced focus errors are clearly observed on wafers of significant film stack variation and/or pattern density variation. Implications on total focus control and depth of focus (DOF) requirements for 65nm mass production are discussed in this paper using a quantitative pattern yield model. The same technique can be extended to immersion lithography.
An automated aberration extraction method is presented which allows extraction of lithographic projection lens' aberration signature having only access to object (mask) and image (wafer) planes. Using phase-wheel targets on a two-level 0/π phase shift mask, images with high sensitivity to aberrations are produced. Zernike aberration coefficients up to 9th order have been extracted by inspection of photoresist images captured via top-down SEM. The automated measurement procedure solves a multi-dimensional optimization problem using numerical methods and demonstrates improved accuracy and minimal cross-correlation. Starting with a detailed procedure analysis, recent experimental results for 193-nm projection optics in commercial full field exposure tools are discussed with an emphasis on the performance of the aberration measurement approach.
The initial experimental verification of a polarization monitoring technique is presented. A series of phase shifting mask patterns produce polarization dependent signals in photoresist and are capable of monitoring the Stokes parameters of any arbitrary illumination scheme. Experiments on two test reticles have been conducted. The first reticle consisted of a series of radial phase gratings (RPG) and employed special apertures to select particular illumination angles. Measurement sensitivities of about 0.3 percent of the clear field per percent change in polarization state were observed. The second test reticle employed the more sensitive proximity effect polarization analyzers (PEPA), a more robust experimental setup, and a backside pinhole layer for illumination angle selection and to enable characterization of the full illuminator. Despite an initial complication with the backside pinhole alignment, the results correlate with theory. Theory suggests that, once the pinhole alignment is corrected in the near future, the second reticle should achieve a measurement sensitivity of about 1 percent of the clear field per percent change in polarization state. This corresponds to a measurement of the Stokes parameters after test mask calibration, to within about 0.02 to 0.03. Various potential improvements to the design, fabrication of the mask, and experimental setup are discussed. Additionally, to decrease measurement time, a design modification and double exposure technique is proposed to enable electrical detection of the measurement signal.