To meet Moore’s law, resist resolution improvement has become more and more important. However, it is difficult to improve resist resolution and keep vertical sidewall profile. For example, a high contrast hole resist may cause trench scum, due to very T-top profile. This paper reports several concepts for resist profile tuning without losing performance for lithographic factor , including mask error enhancement factor (MEEF), depth of focus (DOF), and critical dimension uniformity (CDU). To quantitative analysis the resist profile improvement, we define a new factor, Scum fail ratio (F/R%) for new techniques evaluation. The new techniques, including floatable additive, floatable PAG, and new monomer, are discussed. From X-SEM and CD-SEM data, former three concepts could improve resist sidewall profile quantitatively evaluated by Scum fail F/R% and keep lithographic factors. In addition, another key factor, resist residue defect, is also discussed. The high contrast resist with higher receding contact angle (RCA) easily generates more residue defect after development. With the new monomer composition, RCA of Resist E is decreased from 54 to 48 degree after development. Therefore, the residue defect is improved one order.
For semiconductor manufacturing of k1<0.3 half pitch, immersion lithography is still
indispensable for process development and production. As the minimum feature size reaches the
resolution limit, many resolution enhancement techniques and processes are developed to meet
the stringent imaging requirements. Since the optical contrast is not sufficient for low-k1
application, the optimizing conditions for DOF, MEEF, LWR, 2D features, top-view profile, and
defect become more challenging than ever for manufacturing. The low-k1 induced poor ADI
(after development inspection) end-to-end profile is deleterious to pattern fidelity that may
further impact the AEI (after etching inspection).
From a previous study, the photo-decomposed base (PDB) has been proven effective in
enhancing the resist contrast and improving the DOF from conventional quenchers. In this paper,
we study its further improvement on litho performance by controlling the diffusion lengths of the
PAG and the PDB. We split the polarity and size of the PAG and PDB to control the diffusion
length. The top view profile is improved from rounding to vertical if a longer diffusion length of
the PDB is selected. The scattering bar printing window can also be improved in such a
condition. If the PAG and the PDB have better matching controls, the MEEF, LWR, CDU, and
end-to-end top view profile are improved as shown in Fig.1.
The impact of embedded substrate defects on end-of-line die yield has become significant for advanced process technology nodes. Quality control and grading of wafers intended for leading-edge devices thus require effective detection and identification of embedded defects. In this paper, we present the results of a study on incoming prime-grade wafers using a new defect inspection system capable of dark field scattering and bright field differential interference contrast inspection. The wafers were scanned on a KLA-Tencor Surfscan SP2XP inspection tool, and the combined scan signal were real time analyzed to classify the defects of interest from particles. Inspection of the wafers both before and after a resist-coat process showed that all air pockets detected on the bare substrates resulted in coating defects. In the second part of the study, a set of epitaxial (epi) wafers was inspected using oblique- and normal- incidence dark field scattering as well as bright field differential interference contrast. The defects were classified by rules-based binning, and found to contain a large number of killer defects including epi stacking faults and bumps. Classification results were confirmed by SEM review, and showed that this multi-channel methodology successfully identified the killer defects with >95% accuracy and purity.
Surfactant treatments, with SCR101 and EX01, were applied to both line-space and hole
patterns in this report. 10% Reduction of line-width roughness and the raise of normalized
aspect ratio were observed in line-space patterns after surfactant treatments, compared with
those only treated with DI water. From top-view and cross-section images of hole patterns, it
was found that bottom scum was eliminated and the contact-edge roughness (CER) was also
improved after surfactant treatments. Although 1 to 5% shrinkage of patterns appeared, the
depth of focus (DOF) of hole patterns was still increased due to removal of bottom scum. By
applying the surfactant treatment, we were able to improve not only line width roughness and
collapse margin of line-space patterns, but also CER and DOF of hole patterns.
As the semiconductor feature size continues to shrink, the high NA lithography has become a reality. Coupling with high NA lithography, both the critical dimension control and the insufficient resist thickness for etch mask are becoming major challenges for lithographers. Hence two things are highly desired, one is an effective anti-reflective coating (ARC) strategy to maintain low reflectance for good critical dimension (CD) uniformity (CDU) control, and the other is combined ARC and hard-mask concept to satisfy both lithography and etch performance needs for feature patterning. In this study, a dual dielectric anti-reflective coating (dual-DARC) was first demonstrated as an effective ARC for contact application with high NA lithography. The ordinary single DARC is very sensitive to the thickness variation of underlying films, resulting in a >45nm contact CD variation at interlayer dielectric (ILD) thickness variation of ±150nm induced by CMP process. Unlike the single DARC, the dual-DARC performs a less CD variation of ~5nm at the same film thickness variation. By extending the dual-DARC concept to combined ARC/hard-mask application to contact and poly patterning, several ARC/hard-mask schemes were compared by reflectance control, CD uniformity control and etch hard-mask performance. Apart from the good reflectance and CD uniformity control of dual-DARC-like schemes, the most attractive is that the proper use of dual-DARC concept to hard-mask application, the tight thickness control is not necessary for the bottom layer and you can just tailor the bottom layer's thickness to meet the individual process needs.