As semiconductor technology nodes keep shrinking, ever-tightening on-product overlay (OPO) budgets coupled with continuous process development and improvement make it critical to have a robust and accurate metrology setup. Process monitoring and control is becoming increasingly important to achieve high yield production. In recently introduced advanced overlay (OVL) systems, a supercontinuum laser source is applied to facilitate the collection of overlay spectra to increase measurement stability. In this paper, an analysis methodology has been proposed to couple the measured overlay spectra with overlay simulation to extract exact process information from overlay spectra. This paper demonstrates the ability to use overlay spectra to capture and quantify process variation, which in turn can be used to calibrate the simulation stacks used to create the SCOL (scatterometry-based overlay) and AIM overlay metrology targets, and can be fed into the fab for process monitoring and improvement.
Shrinking on-product overlay (OPO) budgets in advanced technology nodes require more accurate overlay measurement and better measurement robustness to process variability. Pupil-based accuracy flags have been introduced to the scatterometry-based overlay (SCOL) system to evaluate the performance of a SCOL measurement setup. Wavelength Homing is a new robustness feature enabled by the continuous tunability of advanced SCOL systems using a supercontinuum laser light source in combination with a flexible bandpass filter. Inline process monitoring using accuracy flags allows for detection, quantification and correction of shifts in the optimal measurement wavelength. This work demonstrates the benefit of Wavelength Homing in overcoming overlay inaccuracy caused by process changes and restoring the OPO and residual levels in the original recipe.
In recent years, lithographic printability of overlay metrology targets for memory applications has emerged as a significant issue. Lithographic illumination conditions such as extreme dipole, required to achieve the tightest possible pitches in DRAM pose a significant process window challenge to the metrology target design. Furthermore, the design is also required to track scanner aberration induced pattern placement errors of the device structure. Previous workiii, has shown that the above requirements have driven a design optimization methodology which needs to be tailored for every lithographic and integration scheme, in particular self-aligned double and quadruple patterning methods. In this publication we will report on the results of a new target design technique and show some example target structures which, while achieving the requirements specified above, address a further critical design criterion – that of process resilience.