The mask is a known contributor to intra-field fingerprints at the wafer level. Traditionally, a 3σ distribution of critical dimensions (CDs) on mask was considered sufficient to characterize the contribution to the CD distribution at wafer level. Recent studies report wafer local CD distributions characterized for statistics beyond 3σ<sup>1</sup>. Mask has been shown to contribute to wafer local CD distribution also which is typically quantified as Local CD Uniformity (<i>LCDU</i>), a 3σ metric<sup>2</sup>. Additionally, the local placement distribution on wafer could be a contributor to Edge Placement Error <i>(EPE)</i><sup>3</sup>. Consequently, it is imperative to understand, characterize and ultimately control the mask contributions to local CD and placement distribution at wafer level. This work is an investigation of local CD and placement distribution on an EUV mask and its impact on distributions at wafer level.
The mask is a known contributor to intra-field and local patterning fingerprints at the wafer level. Traditionally, a 3σ distribution of critical dimensions (CDs) on mask was sufficient to characterize the contribution to the CD distribution at wafer level. However, as edge placement error (EPE) and EUV wafer patterning stochastics become critical with decreasing feature sizes, wafer CD distributions are being characterized for statistics beyond 3σ. Additionally, Local Placement Error (LPE) is a critical metric that is expected to contribute to EPE. Consequently, it is imperative to understand, characterize and control the EUV mask contributors to the EPE budget. This work is an attempt to extensively characterize the CD and LPE distribution on an EUV mask and identify its impact at wafer level.
YieldStar (YS) is an established ASML-built scatterometer that is capable of measuring wafer Critical Dimension (CD),
Overlay and Focus. In a recent work, the application range of YS was extended to measure 3D CD patterns on a reticle
(pattern CD, height, Side Wall Angle-SWA). The primary motivation for this study came from imaging studies that
indicated a need for measuring and controlling reticle 3D topography.
CD scanning electron microscope (CD-SEM), Atomic force microscope (AFM), 3D multiple detector SEM (3D-SEM)
are the preferred tools for reticle metrology. While these tools serve the industry well, the current research to the impact
of reticle 3D involves extensive costs, logistic challenges and increased reticle lead time. YS provides an attractive
alternative as it can measure pattern CD, SWA and height in a single measurement and at high throughput. This work
demonstrates the capability of YS as a reticle metrology tool.
YieldStar (YS) is an ASML-built scatterometry tool with well-established capability to measure wafer Critical Dimension (CD), Overlay and Focus. In a feasibility study, the application range of YS was extended to measure CD patterns in EUV reticles (absorber CD, height, Side Wall Angle-SWA). The measured data compared well with the available data from CD-SEM and AFM. Further the YS measured data was used to mathematically separate the reticle induced fingerprint from the scanner fingerprint.
EUV sources emit a broad band DUV Out-of-Band (OOB) light, in particular, in the wavelength range 100-400 nm. This can cause additional exposure of EUV resists made that are based on a ArF/KrF resist platform. This DUV light is partially suppressed while travelling through the optical path but a non-negligible part of it reaches wafer level and impacts imaging. <p> </p>This is important for imaging at the edges of an image field when fields are printed very close to each other on the wafer (so-called butted fields, with zero field to field spacing). DUV light is reflected from the reticle black border (BB) into a neighboring exposure field on the wafer. This results in a CD change at the edges and in the corners of the fields and therefore has an impact on CD uniformity. Experimental CDU results are shown for 16 nm dense lines (DL) and 20 nm isolated spaces (IS) (N7 logic design features) in the fields exposed at 0 mm and 0.5mm distance on the wafer. Areas close to the edge of the image field are important for customer applications as they often contain qualification and monitoring structures; in addition, limited imaging capabilities in this area may result in loss of usable wafer space. <p> </p>In order to understand and control OOB DUV light, it must be measured in the scanner. DUV measurements are performed in resist using a special OOB reticle coated with Aluminum (Al) having low EUV reflectance and high DUV reflectance. A model for DUV light impact on the imaging is proposed and verified. For this, DUV reflectance data is collected in the wavelengths range 100-400 nm for Al and BB and the ratio of reflectances of these materials is determined for assumed scanner and resist OOB spectra. Also direct BB OOB test is performed on the wafer and compared to Al OOB results. The sensitivity of 16 nm DL and 20 nm IS to OOB light is experimentally determined by means of double exposure test: a wafer with exposed imaging structures undergoes a second flood exposure from a DUV reflective material (Al or BB). <p> </p>Finally, several OOB mitigation strategies are discussed, in particular, suppression of DUV light in the scanner (~3x improvement), recent successes of DUV suppression for 16 nm imaging resist (~1.8x improvement) and DUV reflectance mitigation in the reticle black border (~3.8x). An overview of OOB test results for multiple NXE systems will be shown including systems with new NXE:3350 optics with improved OOB suppression.
In this paper we discuss edge placement error (EPE) for multi-patterning application and compare the EPE budget with the one for EUV single expose application case. These two patterning methods are candidate for the manufacturing of 10-nm and 7-nm logic semiconductor devices. EUV will enable 2D random pattern layout, while in the multi-patterning case a more restricted 1D design layout is needed. For the 1D design approach we discuss the patterning control spacer pitch division resulting in complex multi-layer alignment and EPE optimization strategies. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets. We use 10-nm node experimental data and extrapolate the error budgets towards the 7-nm technology node. The experimental data will be based on NXE:3300B and NXT:1960Bi/NXT:1970Ci exposure systems. The results are compared to the more straightforward alternative of using single expose patterning with EUV for all critical layers.
There are multiple mask parameters that can be tuned to optimize the lithographic performance of the EUV
photo mask. One of them is the absorber height. A reduction of the absorber height allows, for example, a
higher resolution patterning on mask and reduces the OPC needed for shadowing correction. Downside of
a thinner absorber is the increased reflectivity which manifests itself not only in the image field (contrast loss)
but also in the so called light shield area or image border.
The image border is a pattern free (absorber covered) area around the die on the photo mask forming the
transition area between the part on the mask that is completely shielded from the exposure light by the Reticle
Masking (REMA) blades and the die. The image border accommodates the finite REMA placement accuracy
and the half shadow of the REMA blades allowing close spaced die printing on the wafer.
When printing a die at dense spacing, which is common practice in a production environment, the image border
will overlap part of the neighboring die. This causes actinic EUV and DUV out of band light reflection from the
image border exposing the overlapped die area and affecting CD and contrast at the edges of the dies. For a 44
nm thick absorber we found a CD impact of 8 nm for 32 nm dense lines whereas for a 55 nm thick absorber
the effect was 4 nm for 27 nm dense lines. Increasing the die spacing would prevent this unwanted exposure
but results in an unacceptable loss of valuable wafer real estate thereby reducing the yield per wafer and is thus
not a viable manufacturing solution.
Optical Proximity Correction (OPC) using ASML Brion’s Tachyon NXE model at the edges of the die was
proposed as possible solution to this problem. An alternative is to create a so called Black Border: the
reflectivity in the image border is reduced to a sufficiently low level by for example increasing the absorber
thickness, add a special coating or replace the absorber with a low reflective material. The most radical
solution is removal of the absorber and the underlying multilayer down to the low reflective substrate, so-called
In this paper we will present the effects of such a Black Border created by a multilayer etch on features and
their placement on the reticle and the impact on CD of 27 nm dense lines on the wafer. By comparing the wafer
CDU printed with and without Black Border we will determine how well the image border effect is mitigated by
the multilayer etching.
In this paper we will present ASML's holistic approach to lithography for EUV. This total approach combines the
various components needed to achieve the correct on-product demands of our customers in terms of patterning fidelity
across the entire image field and across the entire wafer.
We will start giving a general update on ASML's NXE scanner platform of which the 6<sup>th</sup> NXE:3100 systems is now
being shipped to a leading chipmaker. The emphasis will be on wafer imaging results for various applications such as
flash memory and logic's SRAM. Then we will describe the second holistic component, NXE-computational
lithography, which was developed to speed-up early learning on EUV and to achieve high accuracy on the wafers.
Thirdly, the YieldStar angular-resolved scatterometry tool that supports the scanner's stability was used to characterize
the system and calibrate the models.
The wafer-results reveal in detail predicted imaging effects of NXE lithography and allow a calibration of system
parameters and characterization of hardware components. We will demonstrate mask-induced imaging effects and
propose an improvement of the current EUV blank or mask-making processes.
As leading edge lithography is moving to 2x-nm design rules, lithography control
complements resolution as one of the main drivers and enablers to meet the very
stringent overlay, focus and CD requirements. As part of ASML's holistic
lithography roadmap, ASML is developing several application-specific
optimization and control applications, such as LithoTuner Pattern Matcher and
These applications are all explicitly designed to improve the scanner process
window (overlay, focus, CDU and matching). All these applications have in
common that they require vast amounts of precise, accurate and process robust
wafer data (either taken on product stacks or on so-called monitor wafers).
To provide such essential data in a cost-effective manner, ASML developed a
metrology platform, called YieldStar. This platform is based on an angle-resolved
high-NA scatterometer. It is versatile, as YieldStar's sensor can measure overlay,
CD and focus in a single measurement. Thanks to its high speed, large amounts
of measurements can be quickly collected.
In this paper the latest generation YieldStar is presented, the so-called 200
platform. This YieldStar 200 can be used in a stand-alone configuration (S-200)
or as an integrated module in a lithography track (T-200). First overlay results
show good TMU results without comprising speed. Furthermore, data is shown
that demonstrate YieldStar's capability to reconstruct 3D CD patterns as well.