CMOS imaging has experienced significant developement in the last decades. At the center of this progress lies the pixel, composed of a light sensitive area (photodiode) coupled to a network of transistors. As the pixels sizes shrink, the light sensitive area gets smaller and requires light focusing assistance. To address this issue, microlenses are added to the top of the pixels stack. The microlenses are made of polymer resist transparent to the wavelength of interest. Creating such structures is not straightforward and requires complex process steps, especially when arrays of multiple shapes and sizes are needed. The grayscale approach appears as a promising alternative since this unconventional lithography method can produce variable shapes and sizes in a single lithography step. Mask data preparation is the most critical step for grayscale lithography. A widespread strategy is to experimentally establish the relationship between a given dose (corresponding to a specific chromium density on the mask) and the remaining resist thickness after development. The relationship, also known as contrast curve, is used as a transfer function to compute a suitable mask for the given resist. Our approach is to create a simplified grayscale model able to predict the resist response under any given mask and illumination condition. Using the classic contrast curve approach we have designed a mask composed of sub 5μm patterns and evaluated the resist profile prediction of the contrast curve approach compared to our grayscale model on various patterns including microlenses, pyramids and bowl shapes. Reults show that the contrast curve approach is no longer appropriate when the dimensions reduce below 5μm.
Today’s technology nodes contain more and more complex designs bringing increasing challenges to chip manufacturing process steps. It is necessary to have an efficient metrology to assess process variability of these complex patterns and thus extract relevant data to generate process aware design rules and to improve OPC models. Today process variability is mostly addressed through the analysis of in-line monitoring features which are often designed to support robust measurements and as a consequence are not always very representative of critical design rules. CD-SEM is the main CD metrology technique used in chip manufacturing process but it is challenged when it comes to measure metrics like tip to tip, tip to line, areas or necking in high quantity and with robustness. CD-SEM images contain a lot of information that is not always used in metrology. Suppliers have provided tools that allow engineers to extract the SEM contours of their features and to convert them into a GDS. Contours can be seen as the signature of the shape as it contains all the dimensional data. Thus the methodology is to use the CD-SEM to take high quality images then generate SEM contours and create a data base out of them. Contours are used to feed an offline metrology tool that will process them to extract different metrics. It was shown in two previous papers that it is possible to perform complex measurements on hotspots at different process steps (lithography, etch, copper CMP) by using SEM contours with an in-house offline metrology tool. In the current paper, the methodology presented previously will be expanded to improve its robustness and combined with the use of phylogeny to classify the SEM images according to their geometrical proximities.
SEM images provide valuable information about patterning capability. Geometrical properties such as Critical Dimension (CD) can be extracted from them and are used to calibrate OPC models, thus making OPC more robust and reliable. However, there is currently a shortage of appropriate metrology tools to inspect complex two-dimensional patterns in the same way as one would work with simple one-dimensional patterns. In this article we present a full framework for the analysis of SEM images. It has been proven to be fast, reliable and robust for every type of structure, and particularly for two-dimensional structures. To achieve this result, several innovative solutions have been developed and will be presented in the following pages. Firstly, we will present a new noise filter which is used to reduce noise on SEM images, followed by an efficient topography identifier, and finally we will describe the use of a topological skeleton as a measurement tool that can extend CD measurements on all kinds of patterns.
Si-Photonics is the technology in which data is transferred by photons (i. e. light). On a Photonic Integrated Circuit
(PIC), light is processed and routed on a chip by means of optical waveguides. The Si-Photonics waveguides
functionality is determined by its geometrical design which is commonly curved, skew and non-Manhattan. That is
why printing fidelity is very challenging on photonics patterns.
In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The
first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The
first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool
design and does not need any retargeting step before OPC. We will compare these two flows on various Si-
Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe
that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow
also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also
discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process
window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an
In a previous work, we demonstrated that the current optical proximity correction model assuming the mask pattern to be analogous to the designed data is no longer valid. An extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason, an accurate mask model has been calibrated for a 14-nm logic gate level. A model with a total RMS of 1.38 nm at mask level was obtained. Two-dimensional structures, such as line-end shortening and corner rounding, were well predicted using scanning electron microscopy pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects, and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular.
Recent industrial results around directed self-assembly (DSA) of block copolymers (BCP) have demonstrated the high potential of such technique. One of the main advantages of this method is the reduction of lithographic steps thus leading to cost reduction. At the same time, the associated correction for mask creation must account for the introduction of this new technique maintaining a high level of accuracy and reliability. In order to create a Vertical Interconnect Layer (VIA) layer, graphoepitaxy DSA is the main candidate. The technique relies on the creation of a confinement guide where the BCP can separate into distinct regions and the resulting patterns are etched in order to obtain an ordered contact layer. The printing of the guiding pattern requires a classical lithography and optical proximity correction (OPC) to obtain the best suited guiding pattern for a specific target. Thus it is necessary to perform simulations of the BCP behavior in order to correctly determine contact hole placement. However, most existing models which simulates the BCP phase segregation have a computational cost that is too high and cannot be used to efficiently correct a full layout. In this study, we propose an original compact model that resolves this issue. The model is based on the calculation of the density probability of PMMA (Polymethyl Methacrylate) domain centers (figure 1). It is compared with both rigorous simulations (based on the Otha-Kawasaki model) and experiments as shown in figure 2. For this analysis, test cases are contact shrink and contact multiplication. The number of PMMA domains inside a structure is also discussed and an analytic formula is derived and compared to experiments (figure 3). The overall consistency of the compact model is presented.
For technologies beyond 10 nm, 1D gridded designs are commonly used. This practice is common particularly in the case of Self-Aligned Double Patterning (SADP) metal processes where Vertical Interconnect Access (VIA) connecting metal line layers are placed along a discrete grid thus limiting the number of VIA pitches. In order to create a Vertical Interconnect Access (VIA) layer, graphoepitaxy Directed Self-Assembly (DSA) is the prevailing candidate. The technique relies on the creation of a confinement guide using optical microlithography methods, in which the BCP is allowed to separate into distinct regions. The resulting patterns are etched to obtain an ordered VIA layer.
Guiding pattern variations impact directly on the placement of the target and one must ensure that it does not interfere with circuit performance. To prevent flaws, design rules are set. In this study, for the first time, an original framework is presented to find a consistent set of design rules for enabling the use of DSA in a production flow using Self Aligned Double Patterning (SADP) for metal line layer printing.
In order to meet electrical requirements, the intersecting area between VIA and metal lines must be sufficient to ensure correct electrical connection. The intersecting area is driven by both VIA placement variability and metal line printing variability. Based on multiple process assumptions for a 10 nm node, the Monte Carlo method is used to set a maximum threshold for VIA placement error.
In addition, to determine a consistent set of design rules, representative test structures have been created and tested with our in-house placement estimator: the topological skeleton of the guiding pattern . Using this technique, structures with deviation above the maximum tolerated threshold are considered as infeasible and the appropriate set of design rules is extracted. In a final step, the design rules are verified with further test structures that are randomly generated using percolation in order to emulate a Placed and Routed (P&R) standard cell block.
Looking for the highest density and best performance, the 14nm technological node saw the development of aggressive designs, with design rules as close as possible to the limit of the process. Edge placement error (EPE) budget is now tighter and Reticle Enhancement Techniques (RET) must take into account the highest number of parameters to be able to get the best printability and guaranty yield requirements. Overlay is a parameter that must be taken into account earlier during the design library development to avoid design structures presenting a high risk of performance failure.
This paper presents a method taking into account the overlay variation and the Resist Image simulation across the process window variation to estimate the design sensitivity to overlay. Areas in the design are classified with specific metrics, from the highest to the lowest overlay sensitivity. This classification can be used to evaluate the robustness of a full chip product to process variability or to work with designers during the design library development. The ultimate goal is to evaluate critical structures in different contexts and report the most critical ones.
In this paper, we study layers interacting together, such as Contact/Poly area overlap or Contact/Active distance. ASML-Brion tooling allowed simulating the different resist contours and applying the overlay value to one of the layers. Lithography Manufacturability Check (LMC) detectors are then set to extract the desired values for analysis.
Two different approaches have been investigated. The first one is a systematic overlay where we apply the same overlay everywhere on the design. The second one is using a real overlay map which has been measured and applied to the LMC tools. The data are then post-processed and compared to the design target to create a classification and show the error distribution. Figure:
Today's design for photonics devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles with minimum feature size below 100nm. Industrial manufacturing of such devices requires optimized process window with 193nm lithography. Therefore, Resolution Enhancement Techniques (RET) that are commonly used for CMOS manufacturing are required.
However, most RET algorithms are based on Manhattan fragmentation (0°, 45° and 90°) which can generate large CD dispersion on masks for photonic designs. Industrial implementation of RET solutions to photonic designs is challenging as most currently available OPC tools are CMOS-oriented. Discrepancy from design to final results induced by RET techniques can lead to lower photonic device performance.
We propose a novel sizing algorithm allowing adjustment of design edge fragments while preserving the topology of the original structures. The results of the algorithm implementation in the rule based sizing, SRAF placement and model based correction will be discussed in this paper. Corrections based on this novel algorithm were applied and characterized on real photonics devices. The obtained results demonstrate the validity of the proposed correction method integrated in Inscale software of Aselta Nanographics.
In a previous work  we demonstrated that current OPC model assuming the mask pattern to be analogous to the designed data is no longer valid. Indeed as depicted in figure 1, an extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason an accurate mask model, for a 14nm logic gate level has been calibrated. A model with a total RMS of 1.38nm at mask level was obtained. 2D structures such as line-end shortening and corner rounding were well predicted using SEM pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular, as depicted in figure 2.
Recent industrial results around directed self-assembly (DSA) of block copolymers (BCP) have demonstrated the high potential of this technique [1-2]. The main advantage being cost reduction thanks to a reduced number of lithographic steps. Meanwhile, the associated correction for mask creation must account for the introduction of this new technique, maintaining a high level of accuracy and reliability. In order to create VIA (Vertical Interconnect Layer) layer, graphoepitaxy DSA can be used. The technique relies on the creation of a confinement guides where the BCP can separate into distinct regions and resulting patterns are etched in order to obtain an ordered series of VIA contact. The printing of the guiding pattern requires the use of classical lithography. Optical proximity correction (OPC) is applied to obtain the best suited guiding pattern allowing to match a specific design target.
In this study, an original approach for DSA full chip mask optical proximity correction based on a skeleton representation of a guiding pattern is proposed. The cost function for an OPC process is based on minimizing the Central Placement Error (CPE), defined as the difference between an ideal skeleton target and a generated skeleton from a guiding contour. The high performance of this approach for DSA OPC full chip correction and its ability to minimize variability error on via placement is demonstrated and reinforced by the comparison with a rigorous model. Finally this Skeleton approach is highlighted as an appropriate tool for Design rules definition.
The 14nm node designs is getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. One of the most critical processes is the contact patterning due to the very aggressive design rules and the process window which becomes quickly limited. Despite the large number of RET applied, some hotspot configurations remain challenging. It becomes increasingly challenging to achieve sufficient process windows around the hot spots just using conventional process such as OPC and rule-based SRAF insertion. Although, it might be desirable to apply Inverse Lithography Technique (ILT) on all hot spots to guarantee ideal mask quality. However, because of the high number of hot spots to repair in the design, that solution might be much time consuming in term of OPC and mask processing.
In this paper we present a hybrid OPC solution based on local ILT usage around hot spots. It is named as Local Printability Enhancement (LPE) flow. First, conventional OPC and SRAF placement is applied on the whole design. Then, we apply LPE solution only on the remaining problematic hot spots of the design. The LPE flow also takes into account the mask rules so that it maintains the mask rule check (MRC) compliance through the borders of the repaired hot spot’s areas. We will demonstrate that the LPE flow enlarges the process window around hot spots and gives better lithography quality than baseline. The simulation results are confirmed on silicon wafer where all the hot spots are printed. We will demonstrate that LPE flow enlarges the depth of focus of the most challenging hot spot by 30nm compared to POR conventional solution. Because the proposed flow applies ILT solution on very local hot spot areas, the total OPC run time remains acceptable from manufacturing side.
Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.
Directed self-assembly (DSA) of block copolymers (BCP) is a promising candidate for alternative micro lithography due to its cost effectiveness, its ability to reduce critical dimension and to increase pattern density. For contact layer patterning, grapho-epitaxy combined with cylindrical BCP is a good candidate. While contact shrink has already been a well-controlled process, contact multiplication is still undergoing further studies. In this paper we propose to study the impact of 193i scanner variations on BCP overlay for contact doubling.
Density multiplication and contact shrinkage of patterned templates by directed self-assembly (DSA) of block copolymers (BCP) stands out as a promising alternative to overcome the limitations of conventional lithography. The main goal of this paper is to investigate the potential of DSA to address contact and via levels patterning with high resolution by performing either CD shrink or contact multiplication. Different DSA processes are benchmarked based on several success criteria such as: CD control, defectivity (missing holes) as well as placement control. More specifically, the methodology employed to measure DSA contact overlay and the impact of process parameters on placement error control is detailed. Using the 300mm pilot line available in LETI and Arkema’s materials, our approach is based on the graphoepitaxy of PS-b-PMMA block copolymers. Our integration scheme, depicted in figure 1, is based on BCP self-assembly inside organic hard mask guiding patterns obtained using 193i nm lithography. The process is monitored at different steps: the generation of guiding patterns, the directed self-assembly of block copolymers and PMMA removal, and finally the transfer of PS patterns into the metallic under layer by plasma etching. Furthermore, several process flows are investigated, either by tuning different material related parameters such as the block copolymer intrinsic period or the interaction with the guiding pattern surface (sidewall and bottom-side affinity). The final lithographic performances are finely optimized as a function of the self-assembly process parameters such as the film thickness and bake (temperature and time). Finally, DSA performances as a function of guiding patterns density are investigated. Thus, for the best integration approach, defect-free isolated and dense patterns for both contact shrink and multiplication (doubling and more) have been achieved on the same processed wafer. These results show that contact hole shrink and multiplication approach using DSA is well compatible with the conventional integration used for CMOS technology.
The NXE:3300B is ASML’s third generation EUV system and has an NA of 0.33 and is positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full transmission. Multiple systems have been qualified and installed at customers. The NXE:3300B succeeds the NXE:3100 system (NA of 0.25), which has allowed customers to gain valuable EUV experience. It is expected that EUV will be adopted first for critical Logic layers at 10nm and 7nm nodes, such as Metal-1, to avoid the complexity of triple patterning schemes using ArF immersion. In this paper we will evaluate the imaging performance of (sub-)10nm node Logic M1 on the NXE:3300B EUV scanner. We will show the line-end performance of tip-to-tip and tip-to-space test features for various pitches and illumination settings and the performance enhancement obtained by means of a 1st round of OPC. We will also show the magnitude of local variations. The Logic M1 cell is evaluated at various critical features to identify hot spots. A 2nd round OPC model was calibrated of which we will show the model accuracy and ability to predict hot spots in the Logic M1 cell. The calibrated OPC model is used to predict the expected performance at 7nm node Logic using off-axis illumination at 16nm minimum half pitch. Initial results of L/S exposed on the NXE:3300B at 7nm node resolutions will be shown. An outlook is given to future 0.33 NA systems on the ASML roadmap with enhanced illuminator capabilities to further improve performance and process window.
The objective of this paper is to extend the ability of a more stable overall process control for the 28 nm Metal layer. A method to better control complex 2D-layout structures for this node is described. Challenges are coming from the fact that the structures, which limit the process window are mainly of 2D routing nature and are difficult to monitor. Within the framework of this study the emphasis is on how to predict these process-window-limiting structures upfront, to identify root causes and to assist in easier monitoring solutions enhancing the process control. To address those challenges, the first step is the construction of a reliable Mask-3D and Resist-3D model. Advanced 3Dmodeling allows better prediction of process variation upfront. Furthermore it allows highlighting critical structures impacted by either best-focus shifts or by low-contrast resist-imaging effects, which then will be transferred non-linearly after etch. This paper has a tight attention on measuring the 3D nature of the resist profiles by multiple experimental techniques such as Cross-section scanning electron microscopy methods (X-SEM) and atomic force microscopy (AFM). Based on these measurements the most reliable data are selected to calibrate full-chip Resist-3D model with. Current results show efficient profile matching among the calibrated R3D model, wafer AFM and X-SEM measurements. In parallel this study enables the application of a new metric as result of the resist profiles behavior in function of exposure dose. In addition it renders the importance on the resist shape. Together these items are reflected to be efficient support on process optimization and improvement on the process control.
The low-k1 domain of immersion lithography tends to result in much smaller depths of focus (DoF) compared to prior technology nodes. For 28 nm technology and beyond it is a challenge since (metal) layers have to deal with a wide range of structures. Beside the high variety of features, the reticle induced (mask 3D) effects became non-negligible. These mask 3D effects lead to best focus shift. In order to enhance the overlapping DoF, so called usable DoF (uDoF), alignment of each individual features best focus is required. So means the mitigation of the best focus shift. This study investigates the impact of mask 3D effects and the ability to correct the wavefront in order to extend the uDoF. The generation of the wavefront correction map is possible by using computational lithographic such Tachyon simulations software (from Brion). And inside the scanner the wavefront optimization is feasible by applying a projection lens modulator, FlexWaveTM (by ASML). This study explores both the computational lithography and scanner wavefront correction capabilities. In the first part of this work, simulations are conducted based on the determination and mitigation of best focus shift (coming from mask 3D effects) so as to improve the uDoF. In order to validate the feasibility of best focus shift decrease by wavefront tuning and mitigation results, the wavefront optimization provided correction maps are introduced into a rigorous simulator. Finally these results on best focus shift and uDoF are compared to wafers exposed using FlexWave then measured by scanning electron microscopy (SEM).
KEYWORDS: Scanning electron microscopy, Data modeling, Atomic force microscopy, Calibration, Data centers, 3D modeling, Lithography, Photoresist processing, Double patterning technology, Electron beam lithography
The pursuit of ever smaller transistors has pushed technological innovations in the field of lithography. In order
to continue following the path of Moore’s law, several solutions have been proposed: EUV, e-beam and double
patterning lithography. As EUV and e-beam lithography are still not ready for mass production for 20 nm and 14 nm
nodes, double patterning lithography play an important role for these nodes. In this work, we focus on a Self-Aligned
Double-Patterning process (SADP) which consists of depositing a spacer material on each side of a mandrel exposed
during a first lithography step, dividing the pitch into two, after being transferred into the substrate, and then cutting the
unwanted patterns through a second lithography exposure.
In the specific case where spacers are deposited directly on the flanks of the resist, it is crucial to control its
profile as it could induce final CD errors or even spacer collapse. One possibility to prevent these defects from occurring
is to predict the profile of the resist at the OPc verification stage. For that, we need an empirical resist model that is able
to predict such behaviour.
This work is a study of a profile-aware resist model that is calibrated using both atomic force microscopy
(AFM) and scanning electron microscopy (SEM) data, both taken using a focus and exposure matrix (FEM).
The new generations of photomasks are seen to bring more and more challenges to the mask manufacturer. Maskshops
face two conflicting requirements, namely improving pattern fidelity and reducing or at least maintaining acceptable
writing time. These requirements are getting more and more challenging since pattern size continuously shrinks and data
volumes continuously grows.
Although the classical dose modulation Proximity Effect Correction is able to provide sufficient process control to the
mainstream products, an increased number of published and wafer data show that the mask process is becoming a nonnegligible
contributor to the 28nm technology yield. We will show in this paper that a novel approach of mask proximity
effect correction is able to meet the dual challenge of the new generation of masks.
Unlike the classical approach, the technique presented in this paper is based on a concurrent optimization of the dose and
geometry of the fractured shots. Adding one more parameter allows providing the best possible compromise between
accuracy and writing time since energy latitude can be taken into account as well. This solution is implemented in the
Inscale software package from Aselta Nanographics.
We have assessed the capability of this technology on several levels of a 28nm technology. On this set, the writing time
has been reduced up to 25% without sacrificing the accuracy which at the same time has been improved significantly
compared to the existing process. The experiments presented in the paper confirm that a versatile proximity effect
correction strategy, combining dose and geometry modulation helps the users to tradeoff between resolution/accuracy
and e-beam write time.
The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop
putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival
of EUV tools. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Sub Resolution
Assist Feature (SRAF), and Lithography Friendly Design (LFD) constitute a significant transformation of the design.
These new Computational Lithography applications have become one of the most computationally demanding steps in
the design process. Computing farms of hundreds and even thousands of CPUs are now routinely used to run these
The 28nm node presents many difficulties due to low k1 lithography whereas the 20nm requires double patterning
solutions. In this paper we present a global view of enhanced RET and DFM techniques deployed to provide a robust
28nm node and prepare for 20nm.
These techniques include advanced OPC manipulation through end user IP insertion into EDA software, optimized sub
resolution assist features (SRAF) placement and pixilated OPC. These techniques are coupled with a fast litho print
check, aka LFD, for 28nm P&R.
The pursuit of even smaller transistors has pushed some technological innovations in the field of lithography. In
order to continue following the path of Moore's law, several solutions were proposed: EUV, e-beam and double
patterning lithography. As EUV and e-beam lithography are still not ready for mass production for 20nm and 14nm
nodes, double patterning lithography will play an important role for these nodes. In this work, we had focused on Self-
Aligned Double-Patterning processes which consist in depositing a spacer material on each side of a mandrel exposed
during a first lithography stepmaking the pitch to be divided by two after transfer into the substrate, the cutting of
unwanted patterns being addressed through a second lithography exposure.
In the specific case where spacers are deposited directly on the flanks of the resist, it is crucial to control its
profiles as it could induce final CD errors or even spacer collapse.
In this work, we will first study with a simple model the influence of the resist profile on the post-etch spacer
CD. Then we will show that the placement of Sub-Resolution Assist Features (SRAF) can influence the resist profile and
finally, we will see how much control of the spacer and inter-spacer CD we can achieve by tuning SRAF placement.
The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to
the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve
enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can
be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of
much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which
identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert
the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification.
STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach.
The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach
of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to
achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based
As the OPC scripts become more and more complex for advanced technology nodes, the number of parameters
used to control the convergence increases drastically. This paper does not aim to determine what a "good
convergence criteria" is but rather to review the efficiency of the existing OPC solutions in terms of accuracy
and parameter dependence, to solve simple design layouts. Three different OPC solutions, including a "standard
algorithm", a "local convergence OPC" and a more holistic OPC, are compared on a design containing lines and
line-ends. A cost function is used to determine the quality of the convergence for each type of structure. A map
of convergence (iteration vs OPC Option) will be deduced for each structure.
Source Mask Optimization (SMO) technique is an advanced resolution
enhancement technique with the goal of extending optical lithography
lifetime by enabling low k1 imaging [1,2]. On that purpose, an appropriate
source and mask duo can be optimized for a given design.
SMO can yield freeform sources that can be realized to a good accuracy
with optical systems such as the FlexRay ,. However, it had been
showen that even the smallest modification of the source can impact the
wafer image or the process. Therefore, the pupil has to be qualified, in
order to measure the impact of any source deformation.
In this study we will introduce a new way to qualify the difference
between sources, based on a Zernike polynomial decomposition . Such
a method can have several applications: from quantifying the scanner to
scanner pupil difference, to comparing the source variation depending of
the SMO settings etc. The straighforward Zernike polynomial decomposition
allow us to identify some classic optical issues like coma or lens
To print sub 22nm node features, current lithography technology faces some tool limitations. One
possible solution to overcome these problems is to use the double patterning technique (DPT). The
principle of the double patterning technique is pitch splitting where two adjacent features must be
assigned opposite masks (colors) corresponding to different exposures if their pitch is less than a
predefined minimum coloring pitch. However, certain design orientations for which pattern features
separated by more than the minimum coloring pitch cannot be imaged with either of the two exposures.
In these directions, the contrast and the process window are degraded because constructive
interferences between diffractive orders in the pupil plane are not sufficient. The 22nm and 16nm nodes
require the use of very coherent sources that will be generated using SMO (source mask cooptimization).
Such pixelized sources while helpful in improving the contrast for selected
configurations, can lead to degrade it for configurations which have not been counted for during the
SMO process. Therefore, we analyze the diffractive orders interactions in the pupil plane in order to
detect these limited orientations in the design and thus propose a new double patterning decomposition
algorithm to enlarge the process window and the contrast of each mask.
The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the
art scanner will be limited to a numerical aperture of 1.35. Thus we cannot "simply" apply a shrink factor from
the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions
in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to
enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is
clearly established that early process for these layers will be performed by double patterning technique coupled
with advanced OPC solutions.
In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS)
and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC
solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure
good process control.
This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored
by the French government.
Source Mask Optimization (SMO) technique is an advanced RET with the goal of extending optical lithography lifetime by enabling low k1 imaging [1,2]. Most of the literature concerning SMO has so far focused on PV (process variation) band, MEEF and PW (process window) aspects to judge the performance of the optimization as in traditional OPC . In analogy to MEEF impact for low k1 imaging we investigate the source error impact as SMO sources can have rather complicated forms depending on the degree of freedom allowed during optimization.
For this study we use Tachyon SMO tool on a 22nm metal design test case. A free form and parametric source solutions are obtained using MEEF and PW requirements as main criteria. For each type of source, a source perturbation is introduced to study the impact on lithography performance. Based on the findings we conclude on the choice of freeform or parametric as a source and the importance of source error in the optimization process.
In double patterning technology (DPT), two adjacent features must be assigned opposite colors,
corresponding to different exposures if their pitch is less than a predefined minimum coloring pitch.
However, certain design orientations for which pattern features separated by more than the minimum
coloring pitch cannot be imaged with either of the two exposures. In such cases, there are no aerial
images formed because in these directions there are no constructive interferences between diffractive
orders in the pupil plane. The 22nm and 16nm nodes require the use of pixelized sources that will be
generated using SMO (source mask co-optimization). Such pixelized sources while helpful in
improving the contrast for selected configurations can lead to degraded contrast for configurations
which have not been set during the SMO process. Therefore, we analyze the diffractive orders
interactions in the pupil plane in order to detect limited orientations in the design and thus propose a
decomposition to overcome the problem.
Proc. SPIE. 7638, Metrology, Inspection, and Process Control for Microlithography XXIV
KEYWORDS: Scanning electron microscopy, Optical proximity correction, Metrology, Calibration, Data modeling, Inspection, Process control, Optical lithography, Current controlled current source, Atomic force microscopy
Mask and metrology errors such as SEM (Scanning Electron Microscopy) measurement errors are currently not accounted for when calibrating OPC models. Nevertheless, they can lead to erroneous model parameters therefore causing inaccuracies in the model prediction if these errors are of the same order of magnitude than targeted modeling accuracy. In this study, we used a dedicated design of hundres of features exposed through a Focus Exposure Matrix for the metrology error, we compared the SEM measurements to AFM measurements for as much as 105 features exposed in various process conditions of does and defocus. These data have then been used in a OPC model calibration procedure. We show that the impact of the metrology error is not negligible and demonstrate the importance of taking into account these errors in order to improve the reliability of the OPC models.
Microlens arrays are used on CMOS image sensors to focus incident light onto the appropriate photodiode and thus
improve the device quantum efficiency. As the pixel size shrinks, the fill factor of the sensor (i.e. ratio of the
photosensitive area to the total pixel area) decreases and one way to compensate this loss of sensibility is to improve the
microlens photon collection efficiency. This can be achieved by developing zero-gap microlens processes. One elegant
solution to pattern zero-gap microlenses is to use a grayscale reticle with varying optical densities which locally
modulate the UV light intensity, allowing the creation of continuous relief structure in the resist layer after development.
Contrary to conventional lithography for which high resist contrast is appreciated to achieve straight resist pattern
profiles, grayscale lithography requires smooth resist contrast curve. In this study we demonstrate the efficiency of
grayscale lithography to generate sub-2μm diameter microlens with a positive-tone photoresist. We also show that this
technique is resist and process (film thickness, development normality and exposure conditions) dependent. Under the
best conditions, spherical zero-gap microlenses as well as aspherical and off-axis microlenses, which are impossible to
obtain with the conventional reflow method, were obtained with satisfying process latitude.
At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF)
that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF
at a sufficient level through pitch.
SRAF are generally generated using Rule Based OPC with a different cleaning step to avoid risk of SRAF printing or
conflict with main feature. One of the key challenges of using such a technique is the ability of placing SRAF in random
holes features. The rule based approach cannot treat all the configurations resulting in non-optimal SRAF placement for
certain main feature. On the other hand, Inverse Lithography has shown the ability of generating SRAF at the ideal size
and position (theoretically) 1 and interest of this technique has been proven experimentally 2,3. Nevertheless, this kind of
technique is not yet ready for maskshop due to MRC limitation caused by the pixelated SRAF output, and the important
mask writing time due to the shotcount 4.
In this paper we propose to make a comparison of the two approaches on random 2D features. We will see that Inverse
Lithography permits to keep a sufficient DOF on 2D features configurations where Rule based appears to be limited.
Simulated and experimental results will be presented comparing Rule based, Ideal and MRC constraint SRAF in terms of
DOF and Runtime performance for hole patterning
Double patterning (DP) is one of the main options to print devices with half pitch less than 45nm. The basis of DP is to
decompose a design into two masks. In this work we focus on the decomposition of the contact pattern layer. Contacts
with pitch less than a split pitch are assigned to opposite masks corresponding to different exposures. However, there
exist contact pattern configurations for which features can not be assigned to opposite masks. Such contacts are flagged
as color conflicts. With the help of design of manufacturing (DFM), the contact conflicts can be reduced through
redesign. However, even the state of the art DFM redesign solution will be limited by area constraints and will introduce
delays to the design flow. In this paper, we propose an optical method for contact conflicts treatment. We study the
impact of the split on imaging by comparing inverse lithography technology (ILT), optical proximity correction (OPC)
and source mask co-optimization (SMO) techniques. The ability of these methods to solve some split contacts conflicts
in double patterning are presented.
With the continuous shrinkage of dimensions in the semiconductor industry, the measurement uncertainty is becoming
one of the major component that have to be controlled in order to guarantee sufficient production yield for the next
technological nodes production. Thus, CD-SEM and Scatterometry techniques have to face new challenges in term of
accuracy and subsequently new challenges in measurement uncertainty that were not really taken into account at the
origin of their introduction in production.
In this paper, we will present and discuss results about the accuracy requirements related to key applications for
advanced technological nodes production. Thus, we will present results related to OPC model precision improvement by
using suitable reference metrology model based on the 3D-AFM technique use. An interesting study related to 193 resist
shrinkage during CD-SEM measurement will be also presented and therefore the impact on measurement uncertainty
will be discussed. Finally we will conclude this paper by showing the potential industrial benefits to use a simple but
relevant 3D-AFM reference metrology model use into the semiconductor production environment.
Optical Proximity Correction (OPC) is used in lithography to increase the achievable resolution and pattern transfer
fidelity for IC manufacturing. Nowadays, immersion lithography scanners are reaching the limits of optical resolution
leading to more and more constraints on OPC models in terms of simulation reliability. The detection of outliers coming
from SEM measurements is key in OPC . Indeed, the model reliability is based in a large part on those measurements
accuracy and reliability as they belong to the set of data used to calibrate the model. Many approaches were developed
for outlier detection by studying the data and their residual errors, using linear or nonlinear regression and standard
deviation as a metric .
In this paper, we will present a statistical approach for detection of outlier measurements. This approach consists of
scanning Critical Dimension (CD) measurements by process conditions using a statistical method based on fuzzy CMean
clustering and the used of a covariant distance for checking aberrant values cluster by cluster. We propose to use
the Mahalanobis distance  in order to improve the discrimination of the outliers when quantifying the similarity within
each cluster of the data set.
This fuzzy classification method was applied on the SEM CD data collected for the Active layer of a 65 nm half pitch
technology. The measurements were acquired through a process window of 25 (dose, defocus) conditions. We were able
to detect automatically 15 potential outliers in a data distribution as large as 1500 different CD measurement. We will
discuss about these results as well as the advantages and drawbacks of this technique as automatic outliers detection for
large data distribution cleaning.
In advanced technology nodes, due to accuracy and computing time constraint, OPC has shifted from discrete simulation
to pixel based simulation. The simulation is grid based and then interpolation occurs between grid points. Even if the
sampling is done below Nyquist rate, interpolation can cause some variations for same polygon placed at different
location in the layout. Any variation is rounded during OPC treatment, because of discrete numbers used in OPC output
file. The end result is inconsistency in post-OPC layout, where the same input polygon will give different outputs,
depending on its position and orientation relative to the grid. This can have a major impact in CD control, in structures
like SRAM for example, where mismatching between gates can cause major issue.
There are some workarounds to minimize this effect, but most of them are post-treatment fix. In this paper, we will try to
identify and solve the root cause of the problem. We will study the relationship between the pixel size and the
consistency of post OPC results. The pixel size is often set based on optical parameters, but it might be possible to
optimize it around this value to avoid inconsistency. One can say that the optimization will highly depend on design and
not be possible for a real layout. As the range of pitch used in a design tends to decrease, thanks to fix pitch layouts, we
may optimize pixel size for a full layout.
As we are moving towards the 32nm node and beyond, the tightening of CD control requirements is becoming very challenging for the semiconductor industry. Therefore, year after year the need for accuracy in CD measurement is becoming one of the major components in process control. In order to succeed reaching in a near future the 'true CD' that will guarantee high yield and high performances, the semiconductor industry has to quickly move into a new 'Industrial Reference Metrology Model'. Today the industrial configuration of CD Metrology relies on CD-SEM or Scatterometry techniques depending on the criticality of the level that is measured. Both techniques are challenged and tend to show strong fundamental limitations in term of accuracy when being used in their conventional configuration (conventional ellipsometry or reflectometry for Scatterometry and threshold algorithm for CD-SEM). Therefore a huge effort has to be made on reference metrology inside the industrial semiconductor environment. The calibration of CD-SEM through Pitch standard is definitely not enough because it does not guarantee any accuracy onto CD measurement which is the main output. In the same way, using Scatterometry in the industrial environment without several 'golden' standards that have been calibrated with a true reference technique is also definitely limited for future technological nodes in order to avoid correlation between outputs (CD, height, Sidewall Angle) that will inevitably lead to wrong process window definition and bad process control.
In this paper we will present some experimental results illustrating in practical terms the needs for future CD metrology and the current limitations of industrial techniques. For example, we will talk about emerging 3D multiwires FET devices which require specific 3D metrology. Based on the conclusion which shows the increasingly need for accuracy in the industrial environment, we will discuss about a potential new Reference Metrology Landscape that take into account the limitations of standard industrial techniques (i.e CD-SEM and Scatterometry). These complementary metrology capabilities which will become mandatory in a near future will help the semiconductor industry to corner well with accurate measurement and Reference Metrology inside the fab.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
At 45 and 32 nm nodes, one of the most critical layers is the Contact one. Due to the use of hyper NA imaging, the
depth of focus starts to be very limited.
Moreover the OPC is rapidly limited because of the increase of the pattern density. The limited surface in the dark field
region of a Contact layer mask enforces the edges movement to stop very quickly.
The use of SRAF (Sub Resolution Assist Feature) has been widely use for DOF enhancement of line and space layers
since many technology node. Recently, SRAF generated using inverse lithography have shown interesting DOF
improvement1. However, the advantage of the ideal mask generated by inverse lithography is lost when switching to a
manufacturable mask with Manhattan structures. For SRAF placed in rule based as well as Manhattan SRAF generated
after inverse lithography, it is important to know what their behavior is, in term of size and placement.
In this article we propose to study the placement of scatter-trenches assist features for the contact layer. For this we have
performed process window simulation with different SRAF sizes and distance to the main OPC. These results permit us
to establish the trends for size and placement of the SRAF.
Moreover we have also take a look of the advantages of using 8 surrounding SRAF (4 in vertical - horizontal and 4 at
45°) versus 4 surrounding SRAF. Based on these studies we have seen that there is no real gain of increasing the
complexity by adding additional SRAF.
The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.
One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from
the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error
budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for
OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model.
The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing
has become ever more complex throughout the years so properly modeling this portion of the process has the potential
to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias
can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we
will show results of a new approach that incorporates mask process modeling. We will also show results of testing a
new dynamic mask bias application used during OPC verification.
Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers.
This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process
optimization is done for minimum pitch dense lines.
Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features
(SRAF) to assist the patterning of isolated trenches structures.
Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with
silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement
characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability.
Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF
Several qualification stages are required for new maskshop tools, first step is done by the maskshop internally. Taking
a new writer for example, the maskshop will review the basic factory and site acceptance tests, including CD
uniformity, CD linearity, local CD errors and registration errors. The second step is to have dedicated OPC (Optical
Proximity Correction) structures from the wafer fab. These dedicated OPC structures will be measured by the
maskshop to get a reticle CD metrology trend line.
With this trend line, we can:
- ensure the stability at reticle level of the maskshop processes
- put in place a matching procedure to guarantee the same OPC signature at reticle level in case of any
internal maskshop process change or new maskshop evaluation. Changes that require qualification could
be process changes for capacity reasons, like introducing a new writer or a new manufacturing line, or for
capability reasons, like a new process (new developer tool for example) introduction.
Most advanced levels will have dedicated OPC structures. Also dedicated maskshop processes will be monitored with
these specific OPC structures.
In this paper, we will follow in detail the different reticle CD measurements of dedicated OPC structures for the three
advanced logic levels of the 65nm node: poly level, contact level and metal level. The related maskshop's processes are
- for poly: eaPSM 193nm with a nega CAR (Chemically Amplified Resist) process for Clear Field L/S
(Lines & Space) reticles
- for contact: eaPSM 193nm with a posi CAR process for Dark Field Holes reticles
- for metal1: eaPSM 193nm with a posi CAR process for Dark Field L/S reticles.
For all these structures, CD linearity, CD through pitch, length effects, and pattern density effects will be monitored.
To average the metrology errors, the structures are placed twice on the reticle.
The first part of this paper will describe the different OPC structures. These OPC structures are close to the DRM
(Design Rule Manual) of the dedicated levels to be monitored.
The second part of the paper will describe the matching procedure to ensure the same OPC signature at reticle level.
We will give an example of an internal maskshop matching exercise, which could be needed when we switched from
an already qualified 50 KeV tool to a new 50 KeV tool.
The second example is the same matching exercise of our 65nm OPC structures, but with two different maskshops.
The last part of the paper will show first results on dedicated OPC structures for the 45nm node.
The introduction of immersion lithography in the production phase has been accompanied with high level of defects
compared to standard process on dry lithography. Continuous process optimization allowed us to reduce the defectivity
to dry lithography level. This learning cycle also permitted to improve our knowledge on immersion defectivity
formation. Immersion lithography process cause specific defects type as watermarks, bubbles, extra pattern and swelling
We will report in this article on our latest experiment on the understanding of defects formation during immersion
process. The influence of the track and scanner parameters has been investigated as well as materials issue (resist, topcoat).
Measurements of leaching, receding contact angle and water uptake have been performed in order to correlate
with defect formation. It appears that material, track and scanner parameters play different role on the formation of
specific immersion defects.
Semiconductor manufacturers work hard to shrink critical dimensions in their device architectures and are in the midst of the 45nm node development. Generally, for the 65nm node, critical layers are processed using 193-nm scanners with numerical apertures up to 0.85 and non-immersion technology. It is clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) need to be examined, especially as the industry turns its attention towards the 45-nm technology generation. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported.
In this paper, we report on the progress of development for the 45nm device level lithography with imaging systems >1NA at the Crolles 2 Alliance. Our continued focus is the insertion of an immersion lithography process into an established pilot manufacturing line to support 45nm process development. We will present immersion resist performance, OPC feasibility, process integration, and defectivity comparisons. Finally, conclusions will be made as to the overall readiness of immersion to support 45nm node processing.
As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical
Proximity Correction (OPC) models grows due to the lithographer's need to ensure high fidelity in the mask-
to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum
feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored.
Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These
effects can be used to improve model accuracy and to better predict the final process window. In this paper,
the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types.
Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.
The merits of hyper NA imaging using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is clear. However, the challenge remains CD control at hyper NA and the development of ARC stacks to support not only lithographic response but also device integrations. Extreme off-axis illumination, polarization, and dense pitches of the C045 and C032 nodes show a significant degradation of reflection and CD control and a significant loss of resolution. Consequently, hyper NA patterning requires the development of a new ARC to improve the overall CD control. Thus, a single ARC layer could not ensure the reflectivity condition, and ARC stacks must now be decomposed into two or three components in order to suppress reflectivity through a wide range of incidence angle.
In a previous work, we presented the advantage of using an antireflective based on CVD organic - inorganic stacks. This paper presents an upgrade of this type of stack, applied to 1.2NA imaging. We will show stack reflectivity simulations based on S-matrix approach. The capabilities of the CVD tools have been taken into account in the simulations in order to define a reflectivity process window. We will present 1.2NA lithography with different optimized ARC stacks, comparing potential capability and CD control in conjunction with the immersion lithography for 45 nm and 32 nm nodes.
Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from:
-Static RAM with very aggressive design rules specially at active, poly and contact
-transistor variability control at the chip level
The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm :
-dipole with polarization and regular layout for active level
-dipole with polarization, regular layout and double patterning to cut the line-end for poly level.
These choices have been made based on the printing performances of a 0.17&mgr;m2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.
C045 node (65nm half pitch) technology processes are driving the development of immersion lithography techniques and infrastructures and C032 node (45nm half pitch) is following in its tracks. As semiconductor development enters the arena of low leakage, high-performance devices using immersion lithography, the 45nm hp technology adds more pressure of decreasing pitches and feature sizes using the most cost effective method available. The Crolles2 Alliance is in the first phases of the push for very low k1 193nm lithography for our technology development. Many resolution enhancement techniques are being explored to fill the low k1 realm; including implementation of these techniques and more aggressive integrations to support the device parameters.
However, the early development of 45nm hp node along with the need for better focus and dose control algorithms, imaging of pitches to allow for the packing density will present significant challenges to photolithography even when considering super hyper-NA immersion lithography. Reflectivity variations, thin film interference through the complex film stacks, and increased sensitivity to feature size is posing a challenge for maintaining good and consistent features.
This paper discusses an analysis and early results covering the beginning development of 45nm hp with >1NA immersion lithography. Specifically, parameters such as illumination and enhancement techniques, processing capability, application of OPC at a very low k1, process integration, mask effects, and defectivity as discussed.
In Extreme Ultraviolet Lithography, the electromagnetic modeling of the mask allows to determine the influence of the mask structure on the electromagnetic field. That makes it possible to take into account the presence of a defect modifying the multi-layer stack . This paper presents the results of simulations, performed using a modal method, on the aerial image of the reflected intensity above the resist depending on the position of a defect with respect to an absorber pattern. These simulations allow to consider the influence of a defect not only on top of the structure but also everywhere inside the multilayer. The current method is the MMFE: Modal Method by Fourier Expansion. Modal methods are well adapted for EUV simulation mask due to materials and structure size.
Extreme Ultraviolet (EUV) masks are composed of EUV-reflective regions (multilayer) and of EUV-absorbing regions (patterned areas). The choice of materials for the absorbing stack (i.e. the buffer layer and the absorber layer) is crucial for providing good optical performances. This choice has to take into account three major issues: optical aspects (EUV and DUV performances, aerial image); repair feasibility and technological feasibility (deposition, etching, stripping...); ageing and utilization aspects: stability of the stack, cleaning capability. In this paper, a new absorbing stack A/B is proposed: this stack completely fulfils optical specifications and its total thickness is much lower than those found in the literature, with absorbing materials like TiN, Cr or TaN for instance. This thin thickness enables to reduce shadowing effects, which is particularly interesting for very advanced nodes. Experimental studies were then carried out on this new stack. We focused on two major topics: low temperature deposition and wet etching feasibility of B-material.
In Extreme Ultraviolet lithography, the electromagnetic modeling of the mask allows to determine the influence of the mask structure on the electromagnetic field. That makes it possible for example to analyze the influence of a defect within the multi-layer stack. This paper describes a modeling method of the EUV mask based on the Rayleigh assumptions1. These hypotheses lead to a more restrictive validity domain than rigorous methods like modal methods or Finite Difference Time Domain (FDTD), but is shown in this paper to be usable adapted for EUV mask simulation. Furthermore the simulations are less costly in memory resources and in computing time.
We have studied the ability of ellipsometric spectroscopy to determine slight feature shape variations. In this paper, we show that an optical technique can be a sensitive technique to detect slight profile variations, especially at the top of the features. Simulated results as well as experimental results are presented. A sensitivity metrics, that is better suited to ellipsometric measurements than the conventional mean square error, is proposed. It is used to quantify the sensitivity to measure the feature shape of interest and to examine preferable experimental set-up. Computer simulations and ellipsometry signal libraries have been generated using a common rigorous electromagnetic modal approach (MMFE, Modal Method by Fourier Expansion). Experimental verification has been performed on resist features fabricated using DUV lithography. The ability and sensitivity to measure overhanging profiles such as notched polysilicon gates that are impossible to measure using top-down SEM is also mentioned.