Among available lithography resolution enhancement techniques the Selective Inverse Lithography (SILT) approach
recently introduced by authors  has been shown to provide the largest process window on lower-NA exposure tools
for 65nm contact layer patterning. In present paper we attempt to harness the benefits of source mask optimization
(SMO) approach as part of our hybrid RET. The application of source mask optimization techniques further extends the
life-span of lower-NA 193nm exposure-tools in high volume manufacturing. By including SMO step in OPC flow, we
show that model-based SRAF solution can be improved to approach SILT process variation (PV) band performance.
Additionally to OPC, the complexity of embedded flash designs requires a high degree of exposure tool matching and a
lithography process optimized for topographically different logic and flash areas. We present a method how SMO can be
applied to scanner matching and topography-related optimization.
In order to fulfill the demands of further shrinkage of our mature 90nm logic litho technologies under the constraints of
costs and available toolsets in a 200mm fab environment, a project called "Push to the Limits" was started. The aim ís
to extend the lifetime and capabilities of existing dry 193nm litho toolsets with medium to low numerical aperture,
coupled with the availability of materials and processes which were known to help up CD miniaturization and to shrink
the 90nm logic litho process as far as possible. To achieve this, various options were explored and evaluated, e.g.
optimization of illumination conditions, evaluation of new materials, usage of advanced RET techniques (OPC, LfD,
DfM and ILT) and resolution enhancement by chemical shrink (RELACS®). In this project we demonstrate how we were
able to extend our existing 90nm technology capability, down close to 65nm node litho requirements on most critical
layers. We present overall result in most critical layer generally and specifically on most difficult layer of contact.
Typical contact litho target at 100nm region was enabled, while realization of 90nm ADI target is possible with addition
of new process materials.
Selective Inverse Lithography (ILT) approach recently introduced by authors  has proven to be advantageous for
extending life-span of lower-NA 193nm exposure tools to achieve satisfactory 65nm contact layer patterning. We intend
to find an alternative solution without the need for higher NA tools and advanced light source optimization. In this paper
we explore possible region selection criteria for ILT application based on pitch for a full chip optical proximity
correction (OPC). Through studying the impact of a given selection criteria on runtime, resolution, and the process
window we recommend an optimal combination. With a justified choice of an ILT selection criteria, we construct a
hybrid OPC flow comprising a recursive sequence of direct assist features generation, selective ILT application, layout
repair, model OPC and hot spots screening.
With escalating costs of higher-NA exposure tools, lithography engineers are forced to evaluate life-span extension of
currently available lower-NA exposure tools. In addition to common resolution enhancement techniques such as off-axis
illumination, edge movement, or applying sub-resolution assist features, Inverse Lithography Technology (ILT) tools
available commercially at this moment offer means of extending current in-house tool resolution and enlarging process
window for random as well as periodic mask patterns. In this paper we explore ILT pattern simplification procedures and
model calibration for a range of illumination conditions. We study random pattern fidelity and critical dimension
stability across process window for 65nm contact layer, and compare silicon results for both conventional optical
proximity correction and inverse lithography techniques.
The growing importance of mask simulation in a low-k1 realm is matched by an increasing need for numerical methods
capable of handling complex 3D configurations. Various approximations applied to physical parameters or boundary
conditions allowed a few methods to achieve reasonable run-times. In this work the theoretical foundation and
simulation results of an alternative 3D mask modeling method suitable for OPC simulations are presented. We have
established the throughput and accuracy of the Coupled-Dipole Simulation Method and have compared results to the
rigorous FDTD approach using a test pattern. We will discuss in detail possible approximations needed in order to
accelerate the method's performance.
Including etch-based empirical data during OPC model calibration is a desired yet controversial decision for OPC
modeling, especially for process with a large litho to etch biasing. While many OPC software tools are capable of
providing this functionality nowadays; yet few were implemented in manufacturing due to various risks considerations
such as compromises in resist and optical effects prediction, etch model accuracy or even runtime concern. Conventional
method of applying rule-based alongside resist model is popular but requires a lot of lengthy code generation to provide
a leaner OPC input. This work discusses risk factors and their considerations, together with introduction of techniques
used within Mentor Calibre VT5 etch-based modeling at sub 90nm technology node. Various strategies are discussed
with the aim of better handling of large etch bias offset without adding complexity into final OPC package. Finally,
results were presented to assess the advantages and limitations of the final method chosen.
In the recent year tools for DFM (Design for Manufacturing) addressing the lithographic pattern transfer like LfD have
evolved besides OPC (Optical Proximity Correction) to reduce the time required from design to manufacturing along the
design to mask data preparation flow. The insertion of ORC (Optical Rule Check) after OPC in a separate mask data
preparation step has been commonly adopted in order to successfully meet the ever increasing need of an advanced
technology node like 130nm, 90nm, 65nm and below. Separate simulation runs are normally done for both OPC and
ORC and it is not unusual that different platforms (software, hardware or algorithm) are used for OPC and ORC,
especially for better ORC processing throughput. An investigation has been made to look into the possibility of a DFMlite
approach by inserting ORC into the OPC run on the same Calibre platform. This is accomplished by adding
additional intelligence necessary to provide a 'polishing' step for a hotspot identified, without increasing the combined
cycle time but having the benefit of both full OPC and partial ORC in a single simulation run.
In today's semiconductor industry downscaling of the IC design puts a stringent requirement on pattern overlay control. Tighter overlay requirements lead to exceedingly higher rework rates, meaning additional costs to manufacturing. Better alignment control became a target of engineering efforts to decrease rework rate for high-end technologies. Overlay performance is influenced by known parameters such as "Shift, Scaling, Rotation, etc", and unknown parameters defined as "Process Induced Variation", which are difficult to control by means of a process automation system. In reality, this process-induced variation leads to a strong wafer to wafer, or lot to lot variation, which are not easy to detect in the mass-production environment which uses sampling overlay measurements for only several wafers in a lot. An engineering task of finding and correcting a root cause for Process Induced Variations of overlay performance will be greatly simplified if the unknown parameters could be tracked for each wafer. This paper introduces an alignment performance monitoring method based on analysis of automatically generated "AWE" files for ASML scanner systems. Because "AWE" files include alignment results for each aligned wafer, it is possible to use them for monitoring, controlling and correcting the causes of "process induced" overlay performance without requiring extra measurement time. Since "AWE" files include alignment information for different alignment marks, it is also possible to select and optimize the best alignment recipe for each alignment strategy. Several case studies provided in our paper will demonstrate how AWE file analysis can be used to assist engineer in interpreting pattern alignment data. Since implementing our alignment data monitoring method, we were able to achieve significant improvement of alignment and overlay performance without additional overlay measurement time. We also noticed that the rework rate coming from alignment went down and stabilized at quite satisfactory level.
Optical & process model are used in conjunction with Mentors Calibre OPC tool to predict the behavior of a lithography process. Resist models rely exclusively on empirical measurement data, while optical models are calibrated based on the users knowledge of tool settings, but also fitting unknown parameters to empirical measurements. The final OPC model is a combination of optical & process behaviors prediction which includes resist & other process influence to meet the ever increasing demand of advanced lithography technology nodes like 90nm & below on model accuracy. Reliance of optical model creation on empirical measurement data is undoubtedly raising suspicion of how well the derived diffraction model is able to provide an accurate description of how light energy is distributed inside the resist. Various work & effort had been conducted in the past to cover defocus phenomenal on final model outcome & methodology introduced on better prediction from defocus to achieve better simulation quality, investigation has been carried out to study in further detail of existing strategy of resist & optical decoupling methodology in this work.
We report a non-destructive in-line monitoring method developed for Cd diffusion into InP on SACM-APD structure. Photocurrent vs voltage measurement are taken directly via proving diffused diodes on a wafer. We demonstrate that there is linear correlation between punch-through voltages Vpt on the photo I-V curves and diffusion depth measured by SIMS and Polaron profiles. It has been established that Vpt can be extracted easily from I-V curves and used for re-diffusion to approach target depth.