We demonstrate high volume manufacturing feasibility of 7 nm technology overlay correction requirement. This stateof- the-art overlay control is achieved by (i) overlay sampling optimization and advanced modeling, (ii) alignment and advanced process control optimization, (iii) multiple target overlay optimization, and (iv) heating control. We will also discuss further improvements in overlay control for 7 nm technology node and beyond including computational metrology, extreme ultraviolet and optic tools overlay matching control, high order alignment correction, tool stability improvement, and advanced heating control.
Wafers at FBEOL layers traditionally have higher stress and larger alignment signal variability. ASML’s ATHENA sensor based scanners, commonly used to expose FBEOL layers, have large spot size (~700um). Hence ATHENA captures the signal from larger area compared to the alignment marks which are typically ~40um wide. This results in higher noise in the alignment signal and if the surrounding areas contain periodic product structures, they interfere with the alignment signal causing either alignment rejects or in some cases- misalignment. SMASH alignment sensors with smaller spot size (~40um) and two additional probe lasers have been used to improve alignment quality and hence reduce mark/wafer rejects. However, due to the process variability, alignment issues still persist. For example, the aluminum grain size, alignment mark trench deposition uniformity, alignment mark asymmetry and variation in stack thicknesses all contribute to the alignment signal variability even within a single wafer. Here, a solution using SMASH sensor that involves designing new alignment marks to ensure conformal coating is proposed. Also new techniques and controls during coarse wafer alignment (COWA) and fine wafer alignment (FIWA) including extra controls over wafer shape parameters, longer scan lengths on alignment marks and weighted light source between Far Infra-Red laser (FIR) and Near Infra-Red (NIR) for alignment are presented. All the above mentioned techniques, when implemented, have reduced the wafer alignment reject rate from around 25% to less than 0.1%. Future work includes mark validation based on the signal response from the various laser colors. Finally, process monitoring using alignment parameters is explored.
With continuous shrink in feature dimensions, overlay tolerance for fabrication of transistors is getting more stringent. Achieving good overlay is extremely critical in getting good yield in HVM environment. It is widely understood that good alignment during exposure is critical for better on product overlay . Conventional methods to choose alignment marks on ASML scanners are based on comparing alignment key performance indicators (KPIs) including signal quality, grid repeatability, etc. It is possible that even with good alignment KPIs, OPO is still impacted. In this paper, we propose aspects that need to be monitored to choose proper alignment marks. LIS (Litho In-Sight) alignment, Ideal overlay/APC parameter signatures are used to determine and validate wafer alignment. LIS alignment ‘Target and Profile selection’ analysis enables us to determine best alignment strategy between multiple strategies/marks based on overlay measurements. Analysis includes examining wafer to wafer OPO variation which is key indicator for alignment robustness. Varying overlay parameters within lot would indicate either large process instability or alignment mark signal instability. It is possible that alignment marks depending on their segmentation can be very differently impacted with the process. Ideal overlay/APC signature stability indicates healthy process and wafer alignment. Having similar APC signatures at corresponding layers would mean that there is no major process or alignment issue.
To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF). The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.
In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the “sample plan” of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.
In this paper we will present the comparison study of these two methods on programmed errors of critical layers of 14nm technology node. Programmed OVL errors were made on certain fields during the exposure. Full coverage OVL measurements were performed using both IBO and DBO. Linear, HOPC and iHOPC modeling has been done from non-programmed fields. Then modeling has been subtracted from these certain programmed fields, and Reticle contribution was also calculated and subtracted. In this study, metrology measurement accuracy and stability can be feasible and more accurate OVL control is enabled by selecting better OVL measurement techniques.
We analyze performance of different customized models on baseliner overlay data and demonstrate the reduction in overlay residuals by ~10%. Smart Sampling sets were assessed and compared with the full wafer measurements. We found that performance of the grid can still be maintained by going to one-third of total sampling points, while reducing metrology time by 60%. We also demonstrate the feasibility of achieving time to time matching using scanner fleet manager and thus identify the tool drifts even when the tool monitoring controls are within spec limits. We also explore the scanner feedback constant variation with illumination sources.
We demonstrate a cost-effective automated rule based sparse sampling method that can detect the spatial variation of overlay errors as well as the overlay signature of the fields. Our technique satisfies the following three rules: (i) homogeneous distribution of ~200 samples across the wafer, (ii) equal number of samples in scan up and scan down condition and (iii) equal number of sampling on each overlay marks per field. When rule based samplings are implemented on the two products, the differences between the full wafer map sampling and the rule based sampling are within 3.5 nm overlay spec with residuals M+3σ of 2.4 nm (x) and 2.43 nm (y) for Product A and 2.98 nm (x) and 3.32 nm (y) for Product B.
With the introduction of N2x and N1x process nodes, leading-edge factories are facing challenging demands of shrinking design margins. Previously un-corrected high-order signatures, and un-compensated temporal changes of high-order signatures, carry an important potential for improvement of on-product overlay (OPO). Until recently, static corrections per exposure (CPE), applied separately from the main APC correction, have been the industry’s standard for critical layers , . This static correction is setup once per device and layer and then updated periodically or when a machine change point generates a new overlay signature. This is a non-ideal setup for two reasons. First, any drift or sudden shift in tool signature between two CPE update periods can cause worse OPO and a higher rework rate, or, even worse, lead to yield loss at end of line. Second, these corrections are made from full map measurements that can be in excess of 1,000 measurements per wafer .
Advanced overlay control algorithms utilizing Run-to-Run (R2R) CPE can be used to reduce the overlay signatures on product in High Volume Manufacturing (HVM) environments. In this paper, we demonstrate the results of a R2R CPE control scheme in HVM. The authors show an improvement up to 20% OPO Mean+3Sigma values on several critical immersion layers at the 28nm and 14 nm technology nodes, and a reduction of out-of-spec residual points per wafer (validated on full map). These results are attained by closely tracking process tool signature changes by means of APC, and with an affordable metrology load which is significantly smaller than full wafer measurements.
There are various data mining and analysis tools in use by high-volume semiconductor manufacturers throughout the industry that seek to provide robust monitoring and analysis capabilities for the purpose of maintaining a stable lithography process. These tools exist in both online and offline formats and draw upon data from various sources for monitoring and analysis. This paper explores several possible use cases of run-time scanner data to provide advanced overlay and imaging analysis for scanner lithography signatures. Here we demonstrate several use-cases for analyzing and stabilizing lithography processes. Applications include high order wafer alignment simulations in which an optimal alignment strategy is determined by dynamic wafer selection, reporting statistics data and analysis of the lot report and the sub-recipe as a sort of non-standard lot report, visualization of key lithography process parameters, and scanner fleet management (SFM)
As photolithography will continue with 193nm immersion multiple patterning technologies for the leading edge HVM process node, the production overlay requirement for critical layers in logic devices has almost reached the scanner hardware performance limit. To meet the extreme overlay requirements in HVM production environment, this study investigates a new integrated overlay control concept for leading edge technology nodes that combines the run-to-run (R2R) linear or high order control loop, the periodic field-by-field or correction per exposure (CPE) wafer process signature control loop, and the scanner baseline control loop into a single integrated overlay control path through the fab host APC system. The goal is to meet the fab requirements for overlay performance, lower the cost of ownership, and provide freedom of control methodology. In this paper, a detailed implementation of this concept will be discussed, along with some preliminary results.
As leading edge lithography moves to advanced nodes in high-mix, high-volume manufacturing environment, automated control of critical dimension (CD) within wafer has become a requirement. Current control methods to improve CD uniformity (CDU) generally rely upon the use of field by field exposure corrections via factory automation or through scanner sub-recipe. Such CDU control methods are limited to lithography step and cannot be extended to etch step. In this paper, a new method to improve CDU at post etch step by optimizing exposure at lithography step is introduced. This new solution utilizes GLOBALFOUNDRIES’ factory automation system and KLA-Tencor’s K-T Analyzer as the infrastructure to calculate and feed the necessary field by field level exposure corrections back to scanner, so as to achieve the optimal CDU at post etch step. CD at post lithography and post etch steps are measured by scatterometry metrology tools respectively and are used by K-T Analyzer as the input for correction calculations. This paper will explain in detail the philosophy as well as the methodology behind this novel CDU control solution. In addition, applications and use cases will be reviewed to demonstrate the capability and potential of this solution. The feasibility of adopting this solution in high-mix, high-volume manufacturing environment will be discussed as well.