As the technology shrinks toward 65nm technology and beyond, Optical Proximity Correction (OPC) becomes more
important to insure proper printability of high-performance integrated circuits. This correction involves some
geometrical modifications to the mask polygons to account for light diffraction and etch biasing. Model-based OPC has
proven to be a convenient, accurate, and efficient methodology. In this method, raw calibration data are measured from
the process. These data are used to build a VT5 resist model  that accounts for all proximity effects that attendant to
the lithography process. To ensure the reliability of the calibrated VT5 model, these data must be broad in the image
parameter space (IPS) to account for different one-dimensional and two-dimensional features for the design intent.
Failure to provide sufficient IPS (i.e. mimic the design intent) coverage during model calibration could result in
marginalizing the VT5 model during OPC, but is difficult to judge when there is enough data volume to safely
interpolate and extrapolate design intent. In this paper we introduce a new metric called Safe Interpolation Distance
(SID). This metric is a multi-dimensional metric which can be used to automatically detect the portions of the target
design that are not covered well by the desired VT5 model.
Model-Based Optical Proximity Correction (MBOPC) is now found in nearly all resolution enhancement recipes
used in leading technology integrated circuit fabrication facilities. Many masks now have critical dimensions less
than the exposure wavelength, which results in light diffraction that distorts the image projected onto the wafer. The
industry is relying more and more on MBOPC to compensate for optical effects that are induced during the exposure
of these masks. The MBOPC operation is usually the highest computational time contributor in the RET flow.
MBOPC procedures include the fragmentation of layout edges longer than a specific value into a number of sub-edges
(fragments). The software engine can move and manipulate each fragment to improve the image transferred to
the wafer. In the sparse MBOPC approach, each fragment receives one or more optical simulation sites, which is a
one-dimensional array of points where light intensity is sampled and calculated. To correctly capture the resist
behavior at each simulation site, there must be enough points to ensure extension of the site to a certain distance
from the fragment. Adding more points beyond this distance does not add any benefit, but can significantly increase
This paper presents an automated method that analyzes layouts for different technology nodes that depend on sparse
simulations as their MBOPC engine, and reports the optimized number of simulation points that need to be in the
simulation site to get the desired accuracy and optimum runtime performance.
Process models are responsible for the prediction of the latent image in the resist in a lithographic process. In order for
the process model to calculate the latent image, information about the aerial image at each layout fragment is evaluated
first and then some aerial image characteristics are extracted. These parameters are passed to the process models to
calculate wafer latent image. The process model will return a threshold value that indicates the position of the latent
image inside the resist, the accuracy of this value will depend on the calibration data that were used to build the process
model in the first place.
The calibration structures used in building the models are usually gathered in a single layout file called the test pattern.
Real raw data from the lithographic process are measured and attached to its corresponding structure in the test pattern,
this data is then applied to the calibration flow of the models.
In this paper we present an approach to automatically detect patterns that are found in real designs and have
considerable aerial image parameters differences with the nearest test pattern structure, and repair the test patterns to
include these structures. This detect-and-repair approach will guarantee accurate prediction of different layout fragments
and therefore correct OPC behavior.