Line pattern collapse (LPC) becomes a critical concern as integrated circuit fabrication continues to advance towards
the 22 nm node and below. Tokyo Electron Limited (TEL) has been investigating LPC mitigation methods for many
years . These mitigation methods include surfactant rinses to help reduce surface tension and Laplace pressures
forces that accompany traditional DIW rinses. However, the ability to explore LPC mitigation techniques at EUV
dimensions is experimentally limited by the cost and availability of EUV exposures. With this in mind, TEL has
adopted a combined experimental and simulation approach to further explore LPC mitigation methods.
Several analytical models have been proposed [2, 3, 4] for a LPC simulation approach. However, the analytical models
based on Euler beam theory are limited in the complexity of profile and material assumptions. Euler beam based
models are also now questionable because they are outside the beam theory's intended aspect ratio regime . The
authors explore the use of finite element models in addition to Euler beam theory based models to understand resist
collapse under typical EUV patterning conditions. The versatility of current finite element techniques allows for
exploration of resist material property effects, profile and geometry effects, surface versus bulk modulus effects, and
rinse and surfactant rinse effects. This paper will discuss pattern-collapse trends and offers critical learning from this
simulation approach combined with experimental results from an EUV exposure system and TEL CLEAN TRACK
ACTTM 12 platform, utilizing state of the art collapse mitigation methods.
Double patterning (DP) techniques are emerging as the dominant method to achieve the 32 nm node and beyond. While
several DP approaches exist, the litho-litho-etch (LLE) process is attractive for reduced manufacturing cost.
Previously published LLE work explored the process latitude in the "positive/negative LLE" regime, wherein the first
resist layer is imaged by positive-tone resist and the second resist layer is imaged in negative-tone.
In this paper, simulation-based techniques are used to determine the process latitude in the "positive/positive LLE"
system. By using the same resist material for first- and second-pass lithography, optical properties are nearly matched.
However, a conformal barrier film or other chemical modification must be applied to inhibit the solubility of the firstpass
topography and maintain immiscibility between layers. The consequences of choosing a positive-tone resist for
both the first- and second-pass are investigated for target CD at 88 nm pitch. Process latitude is characterized using full
resist models, reaction-diffusion kinetic solvers, including diffusion-limiting boundary conditions.
The ever-shrinking circuit device dimensions challenge lithographers to explore viable patterning for the 32 nm halfpitch
node and beyond. Significant improvements in immersion lithography have allowed extension of optical
lithography down to 45 nm node and likely into early 32 nm node development. In the absence of single-exposure
patterning solutions, double patterning techniques are likely to extend immersion lithography for 32 nm node
manufacturing. While several double patterning techniques have been proposed as viable manufacturing solutions, cost,
along with technical capability, will dictate which candidate is adopted by the industry.
Dual-tone development (DTD) has been proposed as a potential cost-effective double patterning technique.1 Dual-tone
development was reported as early as in the late 1990's by Asano.2 The basic principle of dual-tone imaging involves
processing exposed resist latent images in both positive tone (aqueous base) and negative tone (organic solvent)
developers. Conceptually, DTD has attractive cost benefits since it enables pitch doubling without the need for multiple
etch steps of patterned resist layers. While the concept for DTD technique is simple to understand, there are many
challenges that must be overcome and understood in order to make it a manufacturing solution.
This work presents recent advances and challenges associated with DTD. Experimental results in conjunction with
simulations are used to understand and advance learning for DTD. Experimental results suggest that clever processing
on the wafer track can be used to enable DTD beyond 45 nm half-pitch dimensions for a given resist process. Recent
experimental results also show that DTD is capable of printing <0.25 k1-factor features with an ArF immersion scanner.
Simulation results showing co-optimization of process variables, illumination conditions, and mask properties are