This paper describes the development of autonomous electronic micro and nanoscale sensor systems for very harsh downhole oilfield conditions and provides an overview of the operational requirements necessary to survive and make direct measurements of subsurface conditions. One of several significant developmental challenges is selecting appropriate technologies that are simultaneously miniaturize-able, integrate-able, harsh environment capable, and economically viable. The Advanced Energy Consortium (AEC) is employing a platform approach to developing and testing multi-chip, millimeter and micron-scale systems in a package at elevated temperature and pressure in API brine and oil analogs, with the future goal of miniaturized systems that enable the collection of previously unattainable data. The ultimate goal is to develop subsurface nanosensor systems that can be injected into oil and gas well bores, to gather and record data, providing an unparalleled level of direct reservoir characterization. This paper provides a status update on the research efforts and developmental successes at the AEC.
This paper describes the status of 157-nm lithography in mid 2004. With the rapid rise of 193-nm immersion from a potential concept in early 2002 at SPIE, through its development, to scheduled delivery of early production tools in late 2004 and early 2005, 157-nm lithography has taken a backseat in the development of optical lithographic technology. While significant challenges were conquered during the 2000 through 2002 period, the development was too slow to prevent 157-nm from being eclipsed by 193-nm immersion. This work reviews the challenges that were identified and conquered during the development of 157-nm lithography. The jury is still out on potential application to production lithography, although the main development effort has been seriously scaled back. There are still issues that remain to be solved before the technology could evolve into a full manufacturing system. The answer to the question of whether it will evolve or not is left to the future to answer.
Chrome-based absorbers have been the mainstay of the photomask industry for three decades. While chrome is attractive because of its durability and opacity, it conversely poses challenges for etch and repair. Due to large capital investments, any new absorber must be designed to work with existing scanners, mask writers, and mask inspection tools. Furthermore changing absorber materials may not improve defect control in mask blank fabrication, which is a paramount concern in blank fabrication. Consequently, blank manufacturers are reluctant to change from chrome. In terms of return on investment (ROI), the only driver to switch technologies is achieving higher mask and wafer yields. This is a reasonable assumption as both etch and repair tool suppliers believe a non-chrome material like tantalum (Ta) compounds would significantly improve their capabilities with known technologies. A high level estimate shows that with even aggressive improvement assumptions, a 100% conversion from chrome does not save money. Based on the current International SEMATECH (ISMT) cost of ownership (COO) model and improved yields for critical dimension (CD) and defects, a case can be made for converting at and below 100 nm ground rules. An industry wide conversion from chrome to a non-chrome absorber is estimated to cost $100M. By contrast, blank suppliers are reportedly spending "multiple" millions of dollars to improve chrome per year. A widespread concern is whether binary optical masks have enough life left to provide sufficient ROI. Optical lithography will continue to be of use in the foreseeable future. Even as leading-edge production moves to new technology, the main manufacturing volumes will continue to create significant demand for masks for 100 nm to 45 nm for many years. With the industry currently pushing extreme ultraviolet lithography (EUVL), the best situation would be for EUVL and optical lithography to choose the same absorber material. This creates a winning situation for the industry independent of EUVL implementation timing. Today Ta-based films are a reasonable choice.
Mask cleaning has been a significant challenge. Advanced PhotoMasks have proven to be even more difficult. The experimental work on 157nm systems uncovered an issue of particle growth under the pellicle. Since the mask blank had a different composition from existing production mask blanks, there was not a concern about current production impact. Investigations were started after a few incidents occurred on 193nm masks. The investigations demonstrated that the masks have a consistent family of contaminants that are on all chrome absorber masks. The initial work provided clues to the nature of the particle growth and some indication of the potential sources. The issues seemed to evolve from the total system and not a single contaminant source. Currently, hard defects due to particle growth under the pellicle occur industry wide. This paper will provide the methodology employed for a recent cleaning evaluation and identify some of the culprits that cause particle growth. The issue has grown to a major problem and needs to be quickly addressed.
There has been a proliferation of examples of mask cost projections for future ITRS nodes and various technologies. This paper reviews the methodology developed at SEMATECH to insure that projected mask costs reflect the geometries being planned. A detailed description provides the development of the mask manufacturing process and develops a projected cost.
The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor sup-plier community and the manufacturers. INTERNATIONAL SEMATECH has revaluated the projected cost of advanced technology masks. Building on the methodology developed in 1996 for mask costs, this work provided a critical review of mask yields and factors relating to the manufacture of photolithography masks. The impact of the yields provided insight into the learning curve for leading edge mask manufac-turing. The projected mask set cost was surprising, and the ability to provide first and second year cost estimates provided additional information on technology introduction. From this information, the impact of technology acceleration can be added to the projected yields to evaluate the impact on mask costs.
The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. This work examines the impact of technology acceleration on the suppliers, the manufacturers of tools, materials and masks. From an Industry perspective, the development and product life cycle are examined with respect to the resources required and the return on investment. Historical information is available regarding the length of time required to develop a manufacturing worth product. Resource requirement estimates are available, so it is possible to develop an investment curve for product development. Similarly, estimates of total product sales provide the basis of the investment recovery scenario. From these evaluations, the Industry return on investment can be projected. It is possible to evaluate the impact of changes in technology on suppliers as the industry moved from 248nm to 193nm.
The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. This work examines the im-pact of technology acceleration on the manufacturers and the resultant supplier impact. This work begins with an overview of the forces in the industry that are driving the accel-eration. Providing an analysis of the drive behind the acceleration, the impact on total production is developed. This acceleration results in more functionality per unit area in a shorter time frame. Based on a constant growth of devices, the technology acceleration reduces the requirements for manufacturing capacity increases. This fact has a direct im-pact on the supplier community. An additional factor is introduced, which is time to market. An analysis of the impact of "winning" the time to market race provides insight into a key industry driver. This work provides an improved understanding of the market forces that drive the semiconductor industry.
The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. INTERNATIONAL SE-MATECH has been leading and supporting efforts to investigate the impact of the tech-nology introduction. This paper examines the issue of manufacturing tolerances available for image placement on adjacent critical levels (overlay) at the 90nm and 65nm technol-ogy nodes. The allowable values from the 2001 release of the ITRS Roadmap are 32nm for the 90nm node, and 23nm for the 65nm node. Even the 130nm node has overlay requirements of only 46nm. Employing tolerances that can be predicted, the impact of existing production/processing tolerance accumulation can provide an indication of the challenges facing the manufacturer in the production of 90nm and 65nm Node devices.
International SEMATECH has been a focal point for the 157nm effort worldwide. Since beginning the program in 1998, ISMT has provided forums for information dissemination ona semi- annual basis. The ability to develop a consensus to identify the most pressing critical issues has permitted the industry to develop this technology more rapidly than any other has been developed. There are still many issues that remain, but even the unexpected have been addressed and solutions put in place. There is a lesson to be learned that a concerted effort involving the entire industry can provide solutions to even the most difficult problems. The development is not completed, but the end is in sight. 157 nm lithography will be developed faster than any other technology due to the entire industry working in concert.
The Semiconductor Industry has been on a historic productivity growth curve that is due to the feature increase based on size reductions. The pace of technology introduction is accelerating as evidenced by the shortening of time from the introduction of the 180nm node and the introduction of the 130nm node. Historically, the introduction of new nodes had been on a three-year cycle. This raises the question of the impact of this acceleration on the manufacture of masks. This paper examines the impact on semiconductor masks by considering the process steps involved in manufacturing masks and the related cots and cycle time. As technology accelerates, the tools available may not maintain a similar pace of introduction. The consequences of this possible non-compliance with the technology acceleration will have an impact on the cost of masks. An example is employed to demonstrate the financial impact of the technology acceleration. Projections can be made of the continuing impact of technology acceleration on the mask manufacturing process. The conclusions drawn are that several identified, critical processes must be the focus of improvement to allow the industry to continue on the productivity growth curve.
Bulk (or global) heating of photomasks due to e-beam energy deposition during patterning causes thermal expansion of the mask substrate and leads to pattern placement errors. Finite element calculations were performed to simulate the in-plane distortions (IPD) due to the single pass writing of a 6 in. X 6 in. optical reticle. Comparison studies were performed to identify the effects of material properties (such as thermal conductivity and the coefficient of thermal expansion) when pattering SiO<SUB>2</SUB> and CaF<SUB>2</SUB> substrates. Final IPD maps illustrate that thermal distortions of the CaF<SUB>2</SUB> will need to be controlled in order to satisfy increasingly stringent error budgets.
Within the n ext 10 years, sub-100 nm features will be required for state-of-the-industry devices. The tolerances for errors at 100 nm or less are substantially smaller than can be achieved today. A critical element of the error budget is the mask. For the 100 nm generation, the 4x mask image placement requirement is 20 nm with CD requirements as low as 9 nm. The challenge would be significant if the only improvement were to develop superior optical masks. There are multiple advanced technologies that are vying to be the successor to optical lithography. Each of these has a unique mask requirement. The leading contenders for the next generation are 1x x-ray, projection e-beam, ion beam, EUV and cell projection e-beam. The x-ray design is a proximity system that employs a 1x membrane mask. Projection e-beam uses a membrane mask with stabilizing struts. Ion beam lithography employs a stencil membrane mask with a carbon coating. EUV employs a 13 nm radiation source that requires a reflective mask. Cell projection e-beam has 25x or greater image masks that are stitched on the wafer. All the technologies indicated above. Once a total error budget for the mask is known, it is necessary to divide the total into the constituent parts. The major sources of distortion can be categorized into eight areas: mask blank processing, e- beam writing, pattern transfer, pellicle effects, mounting, thermal loadings, dynamic effects during exposure and radiation damage. The distortions introduced by each of these depend upon the type of mask; so, individual mask calculations must be made. The purpose of this paper is to review the modeling requirements of each of the categories and to highlight some results from each of the mask configurations.
The development of the cost of ownership methodology provided the semiconductor industry with a process that is employed to evaluate the life cycle costs of any particular equipment. Applying this technique has provided a cost focus on areas of potential improvement. The existing methodology is equipment centric. The limitation of this process is that there has not been a means of evaluating the impact of the cost of ownership for a process. An evaluation of process requirements indicated that such a tool would provide an advantage for evaluating not only the process flow cost but also allocate the individual cost of ownership values according to the planned volumes and yields. This would not be the comprehensive evaluation that can be done with dynamic simulation, but a static first approximation at total process costs based on a combined process flow. This paper describes the application of this new process to the development of the process cost of ownership to the optical mask production process. The program employed in work, PRO COOL<SUP>TM</SUP>, was developed by WWK in conjunction with SEMATECH. This paper describes the application of process cost of ownership to the optical mask production process sequence. Using a generic mask fabrication flow, process sequence cost of ownership analysis is used to identify cost drivers, throughput limitations, and process cost sensitivities. This generic process flow consists of the data evaluation and general number crunching requirements at the beginning of the process, followed by exposure, develop, inspection, measure, CD, pelliclize, inspect, and ship. Understanding of the relationship of these factors will help evaluate future mask fabrication technologies and requirements. Analyzing a generic optical mask production process sequence showed that the simple approach of adding process step cost of ownership values underestimates the process cost of ownership. Thus a complete analysis must consider the cost of unused capacity in the process sequence. The cost of unused capacity is correlated to the production throughput rate of the bottleneck tool. Capacity analysis helps to identify the bottleneck tool under static conditions, however, process and reliability variation can create short-term bottlenecks which must also be considered.