Double Patterning Technology (DPT) was commonly accepted as the major workhorse beyond water immersion
lithography for sub-38nm half-pitch line patterning before the EUV production. For dense hole patterning, classical DPT
employs self-aligned spacer deposition and uses the intersection of horizontal and vertical lines to define the desired hole
patterns. However, the increase in manufacturing cost and process complexity is tremendous. Several innovative
approaches have been proposed and experimented to address the manufacturing and technical challenges.
A novel process of double patterned pillars combined image reverse will be proposed for the realization of low cost
dense holes in 30nm node DRAM. The nature of pillar formation lithography provides much better optical contrast
compared to the counterpart hole patterning with similar CD requirements. By the utilization of a reliable freezing
process, double patterned pillars can be readily implemented. A novel image reverse process at the last stage defines the
hole patterns with high fidelity.
In this paper, several freezing processes for the construction of the double patterned pillars were tested and compared,
and 30nm double patterning pillars were demonstrated successfully. A variety of different image reverse processes will
be investigated and discussed for their pros and cons. An economic approach with the optimized lithography
performance will be proposed for the application of 30nm DRAM node.
Double exposure (DE) and double patterning (DP) have emerged as leading candidates to fill the technology gap
between water immersion and EUV lithography. Various approaches of them are proposed to achieve 3x-nm half-pitch
dense lines and beyond. Both DE with two resist processes and double patterning (DP) require two separate exposures,
and they are faced very tight overlay margin by the scanner tool. By contrast, self-aligned double patterning (SADP)
requires one exposure only, and provides high feasibility for 3x-nm node at this moment. However, a sequential order of
multiple non-lithographic steps (film deposition, etch, and CMP) cause a complicated and expensive process of SADP.
Instead of using complicated sacrificial layers, the spacers are directly formed at the sidewall of the resist patterns by
low-temperature CVD deposition or spin on sidewall (SoS) material coating. In this paper, lower cost-of-ownership of
SoS material are studied for SADP process.
With recently semiconductor manufacturers Critical Dimension shrink down to 70nm and beyond, I-line layer CD would approach to it's resolution limitation. CD uniformity controling will be
strongly influenced by developing process.
Regarding I-line layer developing process, CD uniformity is always varying with various
developing parameters setting (as nozzle design, developing time, pulse spin, etc).