At 65nm technology node and below, with the ever-smaller process window, it is no longer sufficient to apply traditional
model-based verification at only the nominal condition. Full-chip, full process-window verification has started to
integrate into the OPC flow at the 65nm production as a way of preventing potentially weak post-OPC designs from
reaching the mask making step. Through process-window analysis can be done by way of simulating wafer images at
each of the corresponding focus and exposure dose conditions throughout the process window using an accurate and
predictive FEM model. Alternatively, due to the strong correlation between the post-OPC design sensitivity to dose
variation and aerial image (AI) quality, the study of through-dose behavior of the post-OPC design can also be carried
out by carefully analyzing the AI. These types of analysis can be performed at multiple defocus conditions to assess the
robustness of the post-OPC designs with respect to focus and dose variations. In this paper, we study the AI based
approach for post-OPC verification in detail.
For metal layer, the primary metrics for verification are bridging, necking, and via coverage. In this paper we are mainly
interested in studying bridging and necking. The minimum AI value in the open space gives an indication of its
susceptibility to bridging in an over-dosed situation. Lower minimum intensity indicates less risk of bridging.
Conversely, the maximum AI between the metal lines provides indication of potential necking issues in an under-dosed
At times, however, in a complex 2D pattern area, the location as to where the AI reaches either maximum or minimum is
not obvious. This requires a full-chip, dense image-based approach to fully explore the AI profile of the entire space of
the design. We have developed such an algorithm to find the AI maximums and minimums that will bear true relevance
to the bridging and necking analysis. In this paper, we apply the full-chip image-based analysis to 65nm metal layers.
We demonstrate the capturing of potential bridging or necking issues as identified by the AI analysis. Finally, we show
the performance of the full-chip image-based verification.