A number of new packaging technologies are driving the demand for high performance dual-side alignment (DSA) on 300
mm lithography systems. Advanced system in package (SiP) techniques will require through silicon vias to allow very high
density vertical interchip wiring of multiple device stacks. These through silicon vias need to be freely placed in the device
which creates a requirement for tight registration of the back-to-front side alignment. In the MEMS area, wafer level
packaging is being used for applications where the device must interact with the outside environment without performance
restrictions from the packaging. An example is image sensor chips where the charge-coupled device is on the front side and
the electrical interconnects to the signal processing die are on the back side. This application requires dual-side alignment
on a 300 mm bonded silicon glass sandwich structure.
To support these packaging applications a new lithography stepper capable of dual-side alignment on 300 mm wafers has
been developed. This stepper employs an innovative and flexible system for back-to-front side alignment to support a wide
range of packaging applications. This paper discusses the design and integration of the alignment system on a broad band,
low numerical aperture stepper. Experimental target capture for CMOS image sensor applications is shown. Dual-side
overlay performance data on multiple wafers and lots is reviewed.
The requirements for highly specialized photosensitive materials for nanotechnology and Micro-Electro-Mechanical Systems (MEMS) applications are being driven by the rapid growth of consumer products incorporating these devices. These high volume consumer devices including accelerometers for air-bag sensors, biomedical sensors, optical switches and ink jet print heads. These applications all require ultra-thick photosensitive materials with highly controllable lithographic properties. For ink-jet print head applications, the lithography requirements include the formation of high aspect ratio structures with a negative (re-entrant) profile for nozzle formation. In order to form the required nozzle geometry for high resolution ink-jet printers, photosensitive materials need to be capable of providing up to 10 degree negative profiles at a film thickness of up to 25 microns. For consistent print dot size it is necessary to maintain excellent control and repeatability of the sidewall angle of the nozzle. Since this material remains on the substrate as a permanent part of the ink-jet print head, the mechanical and adhesive properties of the material are as important as the lithographic properties. This paper investigates modifications to an existing MicroChem epoxy-based SU8-4000 thick photoresist to generate highly re-entrant sidewall angles for next-generation high resolution ink-jet nozzle formation. Multiple versions of SU8-4000 with different levels of dye tuned for the exposure wavelength are exposed using a 1X lithography system optimized for thick photoresist processing. This stepper uses a combination of low numerical aperture, broadband exposure and large focus offsets for optimal processing of thick photosensitive materials. Basic photoresist characterization techniques in conjunction with cross sectional SEM analysis are used to establish lithographic capabilities for nozzle formation.
The widespread adoption of advanced packaging techniques is driven by electrical device performance and chip form factor considerations. Flipchip packaging is currently growing at a 25% compound annual rate and it is expected that 90% of all 65 nm logic devices will be bumped. To ensure optimal productivity and cost of ownership, it is imperative to employ lithographic materials that are optimized for these applications and that meet all device specifications.
Bump processing typically has one or more levels that require a permanent layer either to relieve stress on the die (stress buffer layer) or to redistribute electrical connections (redistribution layer). Since these layers remain on the wafer, the mechanical and electrical properties of the material are as important as the lithographic properties. This study will characterize a novel negative, siloxane (Shin-Etsu SINR<sup>(R)</sup>) photoresist for the redistribution and stress buffer application on 300 mm wafers. Siloxanes are a good choice for redistribution and stress buffer layers because of their excellent physical properties, ease of processing and relatively low cure temperatures. The lithographic performance of the SINR is optimized using a broad band, low numerical aperture, 1X stepper. This study evaluates softbake, post exposure bake (PEB), develop conditions and exposure optimization. Due to decreasing feature size at the redistribution level, it is critical to demonstrate CD uniformity and resolution across the entire 300 mm wafer surface. While the CD uniformity data is collected on 300 mm wafers, all process optimization results will be applicable for all standard wafer sizes. The physical properties of the SINR material are evaluated through curing temperature studies and sputtering tests.
Advances in micromachining (MEMS) applications such as optical components, inertial and pressure sensors, fluidic pumps and radio frequency (RF) devices are driving lithographic requirements for tighter registration, improved pattern resolution, and improved process control for pattern placement on both sides of the substrate. Consequently, there is a similar increase in demand for advanced metrology tools capable of measuring the Dual Side Alignment (DSA) performance of lithographic systems.
The requirements for an advanced DSA metrology tool include the capability of measuring points over the entire area of the substrate, and of measuring a variety of different substrates and film types and thicknesses. This paper discusses the precision and accuracy of an advanced DSA metrology system, the UltraMet 100. This system offers DSA registration measurement at greater than 90% of a wafer's surface area, providing a complete front to back side registration evaluation across a wafer. The system uses top and bottom cameras and a pattern recognition system that allow simultaneous target capture and measurement on both substrate surfaces.
Because no industry standard has been established to determine the accuracy of dual side pattern metrology, an accuracy gauge was designed for this study that allows both top and bottom cameras to simultaneously measure offsets between two targets on one substrate surface. In this paper, an accuracy gauge is measured on the UltraMet 100 and the results are compared to measurements taken on a reticle X/Y pattern placement metrology tool calibrated to a NIST traceable standard. In addition, tool performance is analyzed in terms of system repeatability and reproducibility.
The widespread adoption of advanced packaging techniques is driven by device performance and chip form factor considerations. Flip chip packaging is currently growing at a thirty percent compound annual rate and it is expected that in the near future over sixty percent of all 300 mm wafers will be bumped. To ensure optimal productivity and cost of ownership it is imperative to provide lithographic equipment and materials that are optimized for these applications. Due to the constantly shrinking bump pitch, it is critical to show excellent CD uniformity across the entire 300 mm wafer surface for feature sizes as small as 70 microns. Flip chip packaging as well as Nanotechnology (MEMS) applications frequently use one or more very thick photoresist layers for electroplating applications. The plating levels require a photosensitive polymer material capable of coating, exposing and electroplating with conventional equipment and standard ancillary process chemicals. Additionally the process times for coating, baking, exposure and development must be considered since these impacts the overall cost of ownership of the lithography cell. For thick photoresist layers the sidewall profile, plating resistance and postplating stripability are important characteristics. This study will characterize a novel single coat, positive tone photoresist (ShinEtsu SIPR 7120-20) used in electroplating levels up to 100 μm thick on 300 mm wafers exposed with the Ultratech Spectrum 300e<sup>2</sup> stepper and coated and developed with a Steag Hamatech Modutrack system. Process capability is determined by analyzing photoresist film thickness uniformity and critical dimension (CD) control across the wafer. Basic photoresist characterization techniques such as cross sectional SEM analysis are used to establish lithographic capabilities. This study shows excellent adhesion to copper with no surface treatment and no photoresist popping during exposure or post exposure bake (PEB). High aspect ratio, lead-free, solder structures were then electroplated using the optimized photoresist process to demonstrate photoresist durability and stripability.
The performance requirements for ultra-thick photoresists are rapidly increasing with the dramatic growth in lithographic applications that require electroplating processes. Two of the main applications for ultra-thick photoresists are advanced packaging and nanotechnology (MEMS). Flipchip packaging has become widely adopted to address electrical device performance and chip form factor considerations. The growth in the nanotechnology market is driven by a wide range of products, which include accelerometers, ink jet print heads, biomedical sensors and optical switches. The requirements of thick photoresists for solder electroplating are significantly different from typical thin photoresists used in front end of line applications. As the photoresist becomes thicker, processing times increase for many process steps. Photospeed gets slower due to the requirements for more chemical reactions per area of coating. Coating uniformity and edge bead control also become more difficult as photoresist films get thicker and time delay issues between process steps can arise. This result has led to the requirement for special photoresist formulations for thick photoresist films. These are traditionally positive tone DNQ-Novolak materials such as AZ 50XT. Such materials can be designed to work for a particular range of thicknesses, but as the desired thicknesses increases the processing times can become very long for high volume manufacturing. Many new bumping schemes require photoresists in a 60 to 70 μm thickness range. While DNQ-Novolak chemistry can work, there is a desire for faster alternatives to improve total cost of ownership (COO) of the lithography cell. In order to have fast photospeeds and reasonable processing times a chemistry that is very photo efficient is needed. Negative tone cross linking chemistries, which can give tens of thousands of chemical events for one photochemical event, provide excellent photospeed and process times. Positive tone chemically amplified photoresist provide hundreds or thousands of chemical events per photochemical event. They are somewhat slower in photospeed than free radical materials, but still provide reasonable photospeeds.
This paper compares the lithography and processing performance of these two newer types of thick film chemistries with the performance of a state of the art DNQ-Novolak thick film photoresist. The lithographic performance of these three ultra-thick positive photoresists were optimized to control critical dimensions (CD), sidewall angles and aspect ratios. The experimental results includes process latitude studies, electroplating performance and stripping performance. The general result is that negative free radical chemistry has the edge in photo-speed and processing times, but positive photoresist is better for stripping and perhaps for process integration.
Advances in micromachining (MEMS) applications such as optical components, inertial and pressure sensors, fluidic pumps and radio frequency (RF) devices are driving lithographic requirements for tighter registration, improved pattern resolution and improved process control on both sides of the substrate. Consequently, there is a similar increase in demand for advanced metrology tools capable of measuring the Dual Side Alignment (DSA) performance of the
lithography systems. There are a number of requirements for an advanced DSA metrology tool. First, the system should be capable of
measuring points over the entire area of the wafer rather than a narrow area near the lithography alignment targets. Secondly, the system should be capable of measuring a variety of different substrate types and thicknesses. Finally, it should be able to measure substrates containing opaque deposited films such as metals. In this paper, the operation and performance of a new DSA metrology tool is discussed. The UltraMet 100 offers DSA registration measurement at greater than 90% of a wafer's surface area, providing a true picture of a lithography tool’s alignment performance and registration yield across the wafer. The system architecture is discussed including the use of top and bottom cameras and the pattern recognition system. Experimental data is shown for tool repeatability and reproducibility over time.
The performance requirements for ultra-thick photoresists are rapidly increasing due to the dramatic growth of applications such as nanotechnology (MEMS) and advanced packaging. Commercial products such as accelerometers, ink jet print heads, biomedical sensors and optical switches are driving growth in the nanotechnology market. Advanced packaging techniques such as flip chip in package, flip chip in board and wafer level chip scale packaging have become widely adopted to address electrical device performance and chip form factor considerations. The common lithography requirement for these applications is formation of high aspect ratio structures with sufficient process latitude to allow devices to be manufactured in production volumes. The use of a contrast enhancement material (CEM) has been shown to be effective in improving lithographic performance and process latitude for thin photoresist applications. However, CEM technology can also be used for the thick photoresist materials in MEMS and advanced packaging applications. The lithographic performance of three representative thick photoresists was characterized with and without a top CEM. The first two materials are ultra-thick positive photoresists that are widely used for electroplated bump bonding structures. The third material is a thick negative photoresist widely used for electrical redistribution levels. All lithography was performed using a low numerical aperture, 1X stepper to control critical dimensions (CD), sidewall angles and aspect ratios. Cross sectional SEM analysis was used to establish the lithographic capabilities of the three photoresists with and without top CEM. The recommended process flow for each photoresist with top CEM is described. The advantages and disadvantages of using CEM for thick photoresist applications are also discussed.
Pellicles are used in semiconductor lithography to minimize printable defects and reduce reticle cleaning frequency. However, there are a growing number of microlithography applications, such as advanced packaging and nanotechnology, where it is not clear that pellicles always offer a significant benefit. These applications have relatively large critical dimensions and require ultra thick photoresists with extremely high exposure doses. Given that the lithography is performed in Class 100 cleanroom conditions, it is possible that the risk of defects from contamination is sufficiently low that pellicles would not be required on certain process
layer reticles. The elimination of the pellicle requirement would provide a cost reduction by saving the original pellicle cost and eliminating future pellicle replacement and repair costs. This study examines the imaging potential of defects with reticle patterns and processes typical for gold-bump and solder-bump advanced packaging lithography. The test reticle consists of 30 to 90 μm octagonal contact patterns representative of advanced packaging reticles. Programmed defects are added that represent the range of particle sizes (3 to 30 μm) normally protected by the pellicle and that are typical of advanced packaging lithography cleanrooms. The reticle is exposed using an Ultratech Saturn Spectrum 300e<sup>2</sup> 1X stepper on wafers coated with a variety of ultra thick (30 to 100 μm) positive and negative-acting photoresists commonly used in advanced packaging. The experimental results show that in many cases smaller particles continue to be yield issues for the feature size and density typical of advanced packaging processes. For the two negative photoresists studied it appears that a pellicle is not required for protection from defects smaller than 10 to 15 μm depending on the photoresist thickness. Thus the decision on pellicle usage for these materials would need to be made based on the device fabrication process and the cleanliness of a fabrication facility. For the two positive photoresists studied it appears that a pellicle is required to protect from defects down to 3 μm defects depending on the photoresist thickness. This suggests that a pellicle should always be used for these materials. Since a typical fabrication facility would use both positive and negative photoresists it may be advantageous to use pellicles on all reticles
simply to avoid confusion. The cost savings of not using a pellicle could easily be outweighed by the yield benefits of using one.
The performance requirements for ultra-thick photoresists have increased rapidly with the dramatic growth in new lithographic applications that require electroplating processes. Two of the main applications for ultra-thick photoresists are nanotechnology (MEMS) and advanced packaging. Flipchip packaging has become widely adopted to address electrical device performance and chip form factor considerations. The growth in the nanotechnology market is driven by a wide range of products, which include accelerometers, ink jet print heads, biomedical sensors and optical switches. Electroplating levels for these applications require a photosensitive polymer material capable of coating, exposing and plating with conventional semiconductor equipment and standard ancillary process chemicals. A single coat step to achieve the final photoresist thickness is critical to minimize the number of process steps and cycle time. The sidewall profile, aspect ratio, electroplating durability and subsequent stripability are all important. This study characterized a novel positive photosensitive chemically amplified photoresist (ShinEtsu SIPR) for the use in a 65μm thick electroplating level on copper. The lithographic performance of the ultra-thick positive photoresist was optimized using a broad band, low numerical aperture, 1x stepper to control critical dimensions (CD), sidewall angles and aspect ratios. Cross sectional SEM analysis, contrast curves, process linearity, and process latitude plots were used to establish the lithographic capabilities. High aspect ratio structures were then electroplated using the optimized photoresist process to demonstrate photoresist durability and stripability. A recommended process flow is described for this photoresist and stepper.
There are an increasing number of microlithography applications such as advanced packaging, nanotechnology and thin film head production that require the use of thick photoresist materials. The exposure dose requirements for these applications dramatically increase as the photoresist thickness increases. For example, some positive acting novolak photoresists require exposures in excess of 5000 mJoules/cm<sup>2</sup> for 100 μm thick films. When a single reticle is used to pattern many wafers, a significant amount of light and heat energy is transferred from the lithography tool illumination source to the pellicle protecting the reticle image. In high volume production environments, a pellicle can be subjected to accumulated dosages exceeding 500 kJoules/cm<sup>2</sup> within a matter of weeks.
Because thick photoresist applications benefit from using 1X broadband steppers with high wafer plane irradiance, life-testing results were reviewed for broadband pellicles designed for maximum transmission at g, h and i-line wavelengths of Hg. Historically, pellicle lifetime testing was typically carried out only to approximately 500 kJoules/cm<sup>2</sup> . While this test limit may have been sufficient for thin photoresist applications used in semiconductor applications, longer lifetime studies are required to determine pellicle durability for thick photoresist applications.
In this study, life testing was performed on multiple pellicle films designed for broadband illumination, including nitrocellulose, cellulose acetate, cellulose ester and fluoropolymer films. Spectroscopic transmission at g, h and i-line was first measured on unexposed pellicles. The pellicles were attached to test reticles and exposed to high-energy doses on an Ultratech broadband stepper, accumulating up to 3000 kJoules/cm<sup>2</sup> . Transmission was periodically re-measured and the pellicle films were visually inspected for color change and any apparent physical damage. Results were compared to the expected optical properties for each film type, and recommendations are provided for the most appropriate fil type for high-energy applications. Of the six pellicles tested, the two fluoropolymer films showed substantially better transmission stability than the cellulose based films. Discoloration occurred on the cellulose films over the chrome to glass transition area of the test reticle field suggesting that heat in the chrome surface affects the chemical structure of the pellicle films, thereby changing their transmission properties.
The widespread adoption of advanced packaging techniques is primarily driven by electrical device performance and chip form factor considerations. Flip chip packaging is currently growing at a 27% compound annual rate and it is expected that by 2005 over 60% of all 300 mm wafers will be bumped. To ensure optimal productivity and cost of ownership it is imperative to provide lithographic materials that are optimized for these applications. Flip chip packaging frequently uses one or more redistribution levels to increase the number of pads that can be bumped in the minimum form factor. The redistribution level requires a photosensitive dielectric material to be used as a permanent insulating layer. The mechanical, electrical and lithographic properties of the material for this level are all important. This study will characterize a novel photosensitive siloxane material (Shin-Etsu SINRT Photoresist) for the use in the redistribution layer. Siloxanes are a good choice for redistribution because of their excellent physical properties, ease of processing and relatively low curing temperatures. The lithographic performance of SINR photoresist has been optimized using a broad band 1X stepper to control critical dimensions (CD). This study evaluates process capability at multiple exposure wavelengths and post exposure bake (PEB) conditions. Cross sectional SEM analysis, process linearity, Bossung plots and process windows are used to establish the lithographic capabilities. Material modifications also were investigated to control the photoresist sidewall angles.
The acceleration of the International Technology Roadmap for Semiconductors (ITRS) is placing significant pressure on the industry's infrastructure, particularly the lithography equipment. As recently as 1997, there was no optical solution offered past the 130 nm design node. The current roadmap has the 65 nm node (reduced from 70 nm) pulled in one year to 2007. Both 248 nm and 193 nm wavelength lithography tools will be pushed to their practical resolution limits in the near term. Very high numerical aperture (NA) 193 nm exposure tools in conjunction with resolution enhancement techniques (RET) will postpone the requirement for 157 nm lithography in manufacturing. However, ICs produced at 70 nm design rules with manufacturable k 1 values will require that 157 nm wavelength lithography tools incorporate the same RETs utilized in 248nm, and 193 nm tools. These enhancements will include Alternating Phase Shifting Masks (AltPSM) and Optical Proximity Correction (OPC) on F 2 doped quartz reticle substrates. This study investigates simulation results when AltPSM is applied to sub-100 nm test patterns in 157 nm lithography in order to maintain Critical Dimension (CD) control for both nested and isolated geometries. Aerial image simulations are performed for a range of numerical apertures, chrome regulators, gate pitches and gate widths. The relative performance for phase shifted versus binary structures is also compared. Results are demonstrated in terms of aerial image contrast and process window changes. The results clearly show that a combination of high NA and RET is necessary to achieve usable process windows for 70 nm line/space structures. In addition, it is important to consider two-dimensional proximity effects for sub-100 nm gate structures.
The advent of 300 mm wafer processing for semiconductor manufacturing has had a great impact on the development of photolithographic materials, equipment and associated processes. At the same time advanced packaging techniques for these semiconductor devices are making strides for smaller, faster and lower cost parts with improved reliability. Photosensitive polyimides are used for passivation stress buffer relief and soft error protection on almost all memory devices such as DRAM as well as final passivation layers for subsequent interconnect bumping operations on most of today's advanced microprocessors. For processing simplicity and total cost of ownership, it is desirable to use an aqueous developable polyimide to maintain compatibility with standard photoresist processes. This study will investigate the feasibility of processing photosensitive polyimides on 300 mm wafers. The performance of a commercially available, positive acting, aqueous developable polyimide is examined at a thickness appropriate for logic devices. A broadband stepper is utilized since polyimides are highly aromatic polymers that strongly absorb UV light below 350 nm. This stepper exposes photosensitive films using mercury vapor spectrum output from 390 nm to 450 nm (g and h-line) and allows rapid exposure of both broadband as well as narrow spectral sensitive films. The system has been optimized for thick photoresists and polyimides and uses a combination of low numerical aperture with maximum wafer level intensity to achieve well formed images in thick films. Process capability for 300 mm wafers is determined by analyzing polyimide film thickness uniformity and critical dimension (CD) control across the wafer. Basic photoresist characterization techniques such as cross sectional SEM analysis, process linearity and process windows are also used to establish lithographic capabilities. The trade-offs for various process capability windows are reviewed to determine the optimum process conditions for different polyimide applications.
There are a number of new lithographic applications that require the use of ultra-thick photoresists. Extremely large structure heights and high aspect ratios are often necessary for electroplating processes. In this situation it is important for the height of the patterned photoresist to exceed the plating height. Two of the main applications for thick photoresist are micromachining and advanced packaging. Ultra-thick photoresists are used in packaging to define the size and location of the bonds for bump bonding, while in micromachining the photoresist is used to define fluidic chambers and electroforming molds. At photoresist thickness greater than 15 microns, standard lithographic techniques become difficult in terms of performance and productivity. The bake, exposure and develop times increase dramatically as the photoresist thickness climbs. The estimated total process time for a 15 micron photoresist is approximately three times greater than that of a 1 micron photoresist. For thick films the develop time on the wafer track becomes the throughput limiter for the entire lithography cell. Therefore, reducing develop time for thick photoresist processes is critical to enhancing the lithography cell cost of ownership. In this paper we will focus on the developer chemistry and process to improve both performance and productivity for a 15 micron thick photoresist. We evaluate process changes in both normality and surfactant level of the developer. Cross sectional analysis, contrast curves, process linearity and process windows are used to establish the lithographic capabilities. It is clear that a developer and process for a thin photoresist is not necessarily optimum for a thick photoresist process. The implementation of an ultra-thick photoresist becomes more feasible in a manufacturing environment after optimizing developer chemistry and process conditions.
Microlithography applications such as advanced packaging, micromachining and thin film head (TFH) production frequently require the use of thick photoresists and large exposure doses for successful pattern transfer onto substrates. When thick negative acting photoresists are used, exposures as high as 5000mJ/cm2 may be required to maintain the pre-exposure photoresist thickness after develop. In this study, light transmission through photomasks with standard (OD3) and high-density (OD4) Cr films was measured through the ultraviolet spectrum to determine leakage thresholds and evaluate the risk of unwanted exposure with highly sensitive photoresists. Because the higher OD photomasks are the result of an increase in Cr film thickness, photomask process differences, resolution capability and Critical Dimension (CD) uniformity issues were also evaluated. The thicker Cr film could also affect pattern transfer to the wafer. Therefore, resolution and CD uniformity were compared on wafers patterned from both OD3 and OD4 Cr reticles.
The continuos advancement of optical lithography into the regime of sub-100nm patterning capability requires the utilization of shorter exposure wavelengths such as 157nm. This in turn requires modifications in lens performance and stepper body performance. Advances in index homogeneity have made it possible to develop 157nm lens systems suitable for investigating sub-100nm lithography. Recent advances in the transmission of modified fused silica as a reticle material have made it more desirable to pursue 157nm lithography tools. MicroSteppers are a necessary vehicle to obtain photoresist and process information pertaining to the efficacy of this technology for production at the 100nm and 70nm device nodes.
The number of lithographic applications that require the use of ultra-thick photoresists is rapidly increasing. Extremely large structure heights and high aspect ratios are often required for micro-electrodeposition of mechanical components such as coils, cantilevers and valves. These ultra-thick photoresists can also be used as a mold in micromachining (MEMS) applications. Ultra-thick photoresists are also used in bump bond applications to define the size and location of the bonds for advanced packaging. The process optimization required to obtain high aspect ratio structures in ultra-thick photoresist films is extremely challenging. The aspect ratios far exceed those encountered in advanced submicron lithography for integrated circuit (IC) manufacturing. MicroChem's epoxy- based SU-8 thick photoresist, while yielding high performance in the thickness range greater than 100 micrometer, uses organic solvent development and can not be removed using standard stripper chemistries. This process issue limits the use of SU-8 to applications where photoresist removal is not necessary. For this study an experimental chemically- amplified, aqueous-developable, strippable, negative photoresist designated STFN v1 was examined at a thickness of 50 micrometer using a broad band lithography system optimized for thick photoresist processing. This stepper uses a combination of low numerical aperture, high wafer plane irradiance and broadband exposure from 350 to 450 nm for optimal processing of thick photosensitive films. Basic photoresist characterization techniques established for thin films in IC manufacturing are applied to STFN v1 photoresist using a ghi-line lithography system. Cross sectional SEM analysis, process linearity and process windows are used to establish the lithographic capabilities of the photoresist. The performance results for the Strippable STFN v1 photoresist are then compared with the non-strippable material SU-8.
The number of lithographic applications that require the use of photosensitive polyimides is rapidly increasing. The major applications for photosensitive polyimides include flip chip bumping, advanced packaging, passivation stress buffer relief and interlevel dielectric films. The thickness requirements for these applications can vary from less than 1 micron to more than 20 microns. For processing simplicity and total cost of ownership, it is desirable to use an aqueous developable polyimide to maintain compatibility with standard photoresist processes. Optical steppers offer significant advantages for processing thick photosensitive polyimides due to the tighter overlay and improved critical dimension (CD) control possible with these lithography tools versus contact printers or full wafer scanners. A stepper has an additional advantage with thick polyimide structures since the focus can be adjusted at various levels into the film, which will result in improved wall angles and enhanced aspect ratios. For this study the performance of a commercially available, positive acting, aqueous developable polyimide is examined over a range of thicknesses using a novel broadband exposure system. This stepper exposes photosensitive films using the full mercury vapor spectrum output from 350 nm to 450 nm (g, h and i line) and allows rapid exposure of both broadband as well as narrow spectral sensitive films. The system has been optimized for thick photoresists and polyimides and uses a combination of low numerical aperture with maximum wafer level intensity to achieve well formed images in thick films yet offers the advantages of tighter CD control and tight overlay inherent in projection optics. Basic photoresist characterization techniques established for thin films in IC manufacturing are applied to the photosensitive polyimide films. Cross sectional SEM analysis, process linearity and process windows are used to establish relative lithographic capabilities for different polyimide thicknesses and stepper exposure wavelengths. The trade-offs for each of the various process capability windows are reviewed to determine the optimum process conditions for different polyimide applications.
In the photolithographic process, critical dimensions (CD) of exposed features in photoresist need to be controlled to within a specified tolerance related to the nominal feature size. A portion of this tolerance budget is consumed by variations in CD on the photomask. At low k<SUB>1</SUB> factor, a number of parameters in the lithography system impact linearity including lens aberrations, defocus, exposure, partial coherence, and photoresist contrast. The combined effect of these parameters is that errors in the mask CDs are not transferred to the wafer in direct proportion to the optical reduction value of the lithography system. This Mask Error Factor (MEF) becomes a significant problem as it consumes a larger than anticipated portion of the CD tolerance budget. This paper will discuss experimentally evaluated MEF using a 4X i-line stepper for a range of feature sizes from subwavelength to approximately twice the exposure wavelength. A test reticle was built with isolated lines from 200 nm to 600 nm in 12.5 nm increments at 1 X. CD measurements on the reticle were compared to corresponding CD measurements on the wafer in order to establish both linearity and MEF curves for the lithography system. MEF values were also determined across a process window for multiple feature sizes. The MEF was observed to be less than 1.4 for CDs greater than 330 nm (k<SUB>1</SUB> equals 0.5) throughout the process window. However, the MEF rises rapidly to over 3 for CD values smaller than 300 nm (k<SUB>1</SUB> equals 0.45) at nominal focus and exposure. Changes in exposure were not observed to have a noticeable impact on MEF while focus offsets were observed to result in significant increases in MEF. These results indicate that MEF has a much larger impact on focus latitude than on exposure latitude. As a result the process window will be compressed more in focus than in exposure.
Images formed in thick photosensitive materials are widely used as electroplating molds for micro-electromechanical (MEMS) part and other electronic applications such as bump bonding, thin film heads and multichip module manufacturing. The expansion of traditional microelectronic lithography into very thick photoresists present a technical challenge for stepper manufacturers that have traditionally attempted to optimize resolution and depth of focus for thin photoresist systems. Stepper optics and illumination needs to be re-optimized for the best performance in thick photosensitive materials.
The number of lithographic applications that require the use of photoresist thickness of one hundred microns or more is rapidly increasing. Extremely large structure heights and high aspect ratios are often required for micro- electrodeposition of mechanical components such as coils, cantilevers and valves. These ultra-thick photoresist can also be used as a mold in micro-electromechanical systems. Ultra-thick photoresist are also used in bump bond applications to define the size and location of the bonds for advanced flipchip packaging.
The storage space of hard disk drives more than doubles every 18 months. In order to maintain this growth rate, thin film head (TFH) manufacturers continue to seek new technologies to increase the areal density on the magnetic media. The trimming of the track at the rowbar level known as 'pole trimming' has proven itself to be very effective at increasing the number of tracks per inch (TPI) during the inductive head generation. However, the transition to magneto-resistive (MR) head technologies with ever smaller form factors has continued to push the trackwidth (TW) requirements of the industry. Optical proximity correction (OPC) enhanced masks have been used in the semiconductor industry for controlling the shape of contacts and eliminating line shortening effects for submicron features. The TFH industry is facing a similar challenge as TWs dip below 1 micrometer. In an attempt to transition the pole trimming process technology from inductive to MR heads, the issue of magnetic performance versus pattern fidelity of the feature becomes critical. OPC masks can be used to minimize the corner rounding effects of trimmed shared magnetic poles, which are ultimately responsible for the track width. This paper evaluates OPC mask technology on rowbar level pole trimming using a 1X stepper to identify the extendibility of minimum TWs for the MR head generation. Various combinations of serifs were experimentally evaluated at different track widths. Multiple photoresists and photoresist thicknesses were selected to represent the range of processes used in the industry. The experimental results were then compared with photoresist simulation studies of the same OPC reticle features. The validation of the simulation results allowed a wider range of conditions to be studied. The results show that OPC is an effective technique for enhancing pole trimming and extending the areal density of modern head designs.
There is a growing interest in using optical steppers for Micromachining and Microfabrication (MEMS) applications due to the tighter overlay and improved critical dimension (CD) control possible with these lithography tools versus a contact printer or full wafer scanner. MEMS applications frequently require the use of ultra-thick photoresists which can easily exceed fifty microns. Extremely large structure heights and high aspect ratios are often required for micro- electrodeposition of mechanical components such as coils, cantilevers and valves. A stepper has an additional advantage with these structures since the focus can be adjusted at various levels into a thick photoresist, which will result in improved wall angles and enhanced aspect ratios. The patterning of high aspect ratio structures in these ultra- thick photoresist films is extremely challenging. The aspect ratios easily exceed those encountered in submicron lithography for standard integrated circuit (IC) manufacturing. In addition, the specific photoresist optical properties and develop characteristics degrade the CD control for these ultra-thick films. The bulk absorption effect of the photoresist reduces the effective dose at the bottom of the film. This effect is exacerbated by the isotropic wet development process, which produces sloped profiles. Unlike thin photoresist for IC manufacturing, lithography modeling and characterization tools are not available for ultra-thick photoresist films. For this study the performance of several commercially available positive and negative ultra-thick photoresists is examined at a thickness of fifty microns using both high throughput i-line and gh-line lithography systems optimized for thick photoresist processing. The photoresists used in this study are selected to represent the full range of available chemistries available from different suppliers. Basic photoresist characterization techniques created for thin films are applied to the ultra-thick photoresist films. Cross sectional SEM analysis, process linearity and Bossung plots are used to establish relative lithographic capabilities of each photoresist. The trade-offs between the various photoresist chemistries are reviewed and compared with the process requirements for high aspect ratio applications.
There are in increasing number of advanced lithographic technologies that require photoresist film thickness in excess of twenty microns. For example, suppliers of microprocessors are migrating to flip chip packaging because of bond pad limitations. The flip chip application can require photoresist materials as thick as 125 micrometers for the bump-bonding step. Another application that requires ultra- thick photoresist films is micromachining. Extremely large structure heights are frequently required for micro- electrodeposition of the mechanical components such as coils, cantilevers and valves. These applications can require photoresist in excess of a hundred microns thickness. The patterning of high aspect ratio structures in these ultra-thick photoresist films is extremely challenging. The aspect ratios easily exceed those encountered in submicron lithography for standard integrated circuit (IC) manufacturing. In addition, the specific photoresist optical properties and develop characteristics degrade the critical dimension control for these ultra-thick films. The bulk absorption effect of the photoresist reduces the effective dose at the bottom of the film. This effect is exacerbated by the isotropic wet development process which produces sloped profiles. Unlike thin photoresist for IC manufacturing, lithography modeling and characterization are not readily available for ultra-thick photoresist films. The performance of several commercially available positive and negative ultra-thick photoresists is examined over a thickness range of 20 to 100 micrometers . This paper is primarily focused on the 25 micrometers film thickness using both high throughput i-line and gh-line lithography systems optimized for thick film processing. The various photoresists used in this study were selected to represent the full range of available chemistries from multiple suppliers. Basic photoresist characterization techniques for thin films are applied to the ultra-thick photoresist films. The cross sectional SEM analysis and Bossung plots were used to establish relative lithographic capabilities of each photoresist. The trade-offs between the various photoresist chemistries is reviewed and compared with the process requirements for the various applications. A future paper will discus the capabilities of these same photoresists at both 50 and 100 micrometers film thicknesses.
Over the past few years there has been a growing interest in using advanced image formation techniques to enhance optical lithography resolution. Techniques such as Optical Proximity Correction (OPC) and phase shifting involve changes in reticle manufacturing which increase the printability risk of small reticle defects and therefore impact wafer yields. There have been several experimental and simulation studies on the printability of sub-half micron defects using both reduction and 1X photolithography equipment. In general these studies have focused on the printability effects of line and space features. However, OPC is frequently implemented to control the size and shape of contact structures. This study was performed to gain a better understanding of the behavior of contact hole defects in a 1X lithography system using both a moderate and a high contrast photoresist. A test reticle was created with 0.72 micrometer contact holes containing edge, corner and isolated central defects in programmed sizes from 0.15 to 0.4 micrometer, and exposed on a submicron 1X stepper. Printability was determined by measurement of the normalized area of the contact (NCA). Reticle defect printability of the contact structures was modeled for each photoresist using a three-dimensional (3D) optical lithography simulation tool. The experimental NCA data was compared to modeled results to validate the simulator. Cross sectional contact simulations were then prepared to show the relative impact on the placement of the defect in the contact structure. Both the simulation and the experimental results show the relative sensitivity of the two photoresists to the printability of defects in the contact hole structure. This analysis enhances the understanding of the criticality of defect sizes in contact arrays and allows users to predict defect printability issues for new photoresists.
A method has been developed that allows accurate simulation of pattern profiles in photoresist in excess of 10 micrometer thick. The method uses the DEPICT<SUP>R</SUP> photolithography simulator to model i-line exposure, bake and development of Shipley SJR<SUP>R</SUP>5740 thick film photoresists with an Ultratech 2244i Wafer Stepper<SUP>R</SUP>. Kim model inputs were estimated from a family of development rate curves obtained by processing wafers with a range of expose energies for logarithmically increasing develop times and measuring thickness change as the develop process occurred. These results were compared with dissolution results obtained using a laser-based dissolution rate monitor. Uncertainties in the measured photoresist absorbence, photosensitivity and refractive index coefficients were estimated and their influence on the simulated results were considered. An optimization procedure and algorithm that allows quantitative comparison of experimental and simulated photoresist profiles is presented. Simulated photoresist profiles were compared with patterns obtained from processed wafers. As a further test of the models, pattern profiles were simulated for 2 micrometer spaces in 10 micrometer thick photoresist through focus. Experimental and simulated pattern profiles from a range of exposure doses were also compared.
There has been considerable attention given to the printability of reticle defects and their impact on wafer yields. Over the last year the printability risk from small defects increased due to the wider application of optical proximity correction structures and the inclusion of more phase shifting retictles. There have been several simulation studies on the printability of sub-halfmicron defects using lens and illumination parameters of 5X reduction steppers. Since submicron 1X projection systems are being incorporated into numerous fabricant lines, there is a clear need to determine if these system show similar sensitivity to sub- halfmicron defects as reduction steppers. Earlier experimental work examined the printability of several classes of sub-halfmicron 25 micrometers defects on a submicron 1X stepper. To extend this work, a 3D optical lithography simulation tool has been employed to predict the printablity of various reticle defect scenarios. Experimental data was used to validate the 3D simulator by comparing modeling data to SEM measurements of wafers exposed with a reticle containing programmed clear pinhole and opaque pindot defects. A statistically designed simulation study was performed to quantify the critical dimension variation resulting from defects of varying size, proximity to a feature edge and variation in the pitch of the impacted line/space features. An additional statistically designed simulation was then use to predict the printability behavior of defects relative to different features sizes over a range of numerical aperture and partial coherence settings applicable to a 1X lens design. Finally, the impact of defect length and width on printability were characterized for rectangular defects over a range of sizes. Overall, this analysis enhances the understanding of the relationship between reticle defects and 1X projection optics and allows for determination of optical reticle defect specifications for cost effective lithography applications.
As the push for improved resolution in wafer lithography intensifies and 0.18 micrometer devices are nearing production, the potential impact of subhalf micron reticle defects has become a growing concern. There have been several studies on the printability of subhalf-micron defects on high resolution reduction photolithography equipment. These studies have been extended to 1X lithography systems and more recently to advanced sub-micron 1X steppers. Previous studies have indicated that 0.20 micrometer opaque and 0.25 micrometer clear pinhole defects were at the margins of adversely impacting 0.65 micrometer lithography on a 1X stepper. However, due to the limited number of defects at these sizes on the reticle, definitive conclusions on printability could not be drawn. An additional study, using a three dimensional (3D) optical lithography simulation program, has shown defect size, proximity to an adjacent feature, and feature pitch to be significant factors contributing to reticle defect printability. Using the simulation findings as a guide, a new reticle was designed to contain an increased number of clear pinhole and opaque defects in the 0.15 to 0.30 micrometer range located in multiple pitches of both horizontal and vertical line/space pairs. Defect printability was determined using a 1X i-line projection stepper with focus and exposure optimized for nominal critical dimensions of 0.65 micrometer. The reticle and wafer defects were measured using low voltage SEM metrology. Simulation and experimental results have shown that pitch is the most significant contributor in the printability of clear pinhole, opaque, square and aspect ratio defects. In general, the impact of defect proximity to an adjacent feature is less extreme than the effect of pitch, but is more pronounced for clear pinhole defects. This study suggests that simulation can be a useful tool to help lithographers understand the behavior of reticle defects for particular layout design parameters. Consequently, simulation can be used to develop realistic reticle defect specifications with mask vendors, and improve cost-effectiveness. Defect printability simulation can also be used to predict the effect of known defects on existing reticles to determine if these reticles should be used for manufacturing.
There have been several studies on the printability of subhalf-micron defects using reduction steppers. These studies typically involved 1X reticles with defect sizes greater than 0.3 micrometers . Because submicron 1X projection systems are being incorporated into numerous fabrication lines, there is a clear need to determine the impact of subhalf-micron defects using these systems. This paper examines defect detection and measurement capability on 1X reticles and the printability of those defects on production submicron 1X steppers. This analysis will enhance the understanding of the relationship between defect size and 1X projection optics and allows for determination of optimal defect specifications. A test reticle representative of a 64 Mb DRAM metal layer was manufactured with a programmed series of attached and isolated defects ranging from 0.15 to 0.5 micrometers . Both clear and opaque polarity defects were designed. The defects were identified and measured on two different reticle autoinspection systems. The performance of the two systems was compared to the reticle database to evaluate capture rates and efficiency. Actual reticle defect sizes were measured using low voltage SEM metrology. Defect printability was determined using a 1X i-line projection stepper with focus and exposure optimized for nominal critical dimensions (CD). The defects that printed on the wafer were measured and compared to the defects measured on the reticle. The effects of varying wafer exposure dose and focus within a 10 percent CD process window on defect printability were also evaluated. The results of the mask inspection comparison and the reticle versus wafer defect maps are compared.
Modem package designs generate a large amount of stress on the die which can be controlled using a thick film of polyimide over the passivation layer. Polyimide film thicknesses in excess of twenty microns at exposure are becoming common for very thin packages. The standard polyimide lithographic process frequently utilizes a trilayer film consisting of an adhesion layer, a polyimide film, and photoresist. A major advance in polyimide technology occurred with the introduction of photosensitive polyimide materials. These materials reduce the total number of process steps in the polyimide process. They also offer the opportunity to combine the passivation and polyimide lithography steps into one process level resulting in significant process simplification and manufacturing cost reduction. Consequently, there is a rapid increase in the use of photosensitive polyimides in the semiconductor industry. There are a number of important issues associated with photosensitive polyimide processing. Because most photosensitive polyimides are negative tone, residual film formation has a major impact on resolution and the usable process window. The high exposure doses required for thicker polyimide films exacerbates the residual film problem. Also, resolving small features such as fuse windows in DRAMs is frequently required in thick photosensitive polyimide layers. These small features result in polyimide height-to-linewidth aspect ratios that are comparable to many photoresist applications. Because of these requirements, photosensitive polyimide applications could benefit from detailed process characterization to enhance resolution and increase process latitude. Unfortunately, there is scant literature pertaining to lithographic performance and lithographic process modeling for photosensitive polyimide films. An extension of basic photoresist characterization techniques for thin films can be applied to thick photosensitive polyimide processes. The develop rate characteristics and lithographic performance for several commercial photosensitive polyimide products were studied at a thickness of 12 microns. Cross sectional SEM analysis, Bossung plots, and film retention plots are used to establish relative lithographic capabilities. These experimental results are used to study the effects of polyimide physical and chemical properties on lithographic performance.
A crucial aspect of overlay optimization is proper selection of stepper input corrections. Automated metrology systems provide the ability to rapidly amass extensive overlay data on lithography systems and processes. The data can then be used to provide feedback in the form of stepper input correction terms to improve overlay. A common approach is an analysis of the overlay data using conventional grid and lens models to determine apparent corrections to be applied to the stepper. However, the standard models do not necessarily account for all the variability in the measured data. Determination of optimal corrections is further complicated by cross-correlation of the stepper input correctable terms. In these cases, the simple application of the grid and lens modeled terms will not provide optimal results. The use of efficient experimental design techniques can reduce the large uncertainty involved in determining and applying these stepper input corrections. Using traditional experimental factorial and response surface design techniques, a descriptive model was developed for the six grid correction terms. The resulting empirical model was generated by using a six factor Box-Behnken experimental design. Multiple wafers were run at these conditions and overlay was measured using an automated metrology system. This empirical model was used to derive the optimal set of inputs to the stepper. This descriptive model is compared with input settings determined from a conventional grid model.
Mix-and-match lithography continues to gain acceptance as a valuable strategy for reducing capital costs and increasing throughput productivity in semiconductor manufacturing. The successful implementation of mix-and-match lithography requires consideration of the unique characteristics of all systems being matched. Among these issues are alignment target placement and alignment strategy. The alignment system for each stepper manufacturer uses specially designed targets for wafer alignment. However, the wafer area available for dedicated alignment targets is typically restricted to maximize the quantity of production die per wafer. One approach to remove the target area limitation is to implement an alignment system based on pattern recognition techniques.
Semiconductor lithography manufacturing presents a major challenge for the application of classical Statistical Process Control (SPC) methodologies due to the complex nature of this process. For example, difficulties can occur due to inadequate data sampling, nonnormal error distributions, equipment or process instability and nonstationary random errors. Incorrect use of classical SPC techniques can result in the incorrect interpretation of process stability which can have a drastic impact on productivity. Photolithography provides additional SPC challenges due to the inherent multivariable nature of the output variables that are being controlled. This paper examines appropriate SPC and monitoring techniques for stepper control of overlay performance using in-process measurement and analysis equipment to address these issues. The average run length of three charting techniques is compared to quantify the ability of each technique to detect process mean shifts. Shewart, Exponentially Weighted Moving-Average (EWMA) and Cumulative-Sum (CUSUM) charts are analyzed for a baseline process and mean shifts of 0.42, 0.85 and 1.25 standard deviations. These results illustrate the superior performance of a CUSUM chart over Shewart and EWMA charts. In addition, the Shewart chart with Western Electric rules produced false mean shift alarms for the baseline case. The EWMA is also observed to be sensitive to the selection of weighting factors. The effectiveness of plotting individual wafers is compared with plotting lot means. The plotting of individual wafers outperforms lot means in the determination of baseline shifts because of the larger population size of the individual charts.
In this study, the distortion signature of an Ultratech 2244i lens was measured using an advanced registration measurement system. A correction for this distortion signature was applied to the design database and a mix-and-match test reticle fabricated. In order to quantify the effectiveness of this technique, a mix-and-match overlay study was performed using the same Ultratech 2244i and an advanced 5x reduction stepper. Overlay experiments were performed using both corrected and noncorrected reticles on the Ultratech system. An automated metrology system was used to collect overlay measurements distributed over the entire lens field area. Detailed analysis of the lens intrafield component of the overlay error using both reticles illustrates the advantages of applying reticle distortion corrections.
In this study, a large field 1x stepper was matched to an advanced 5x reduction stepper using a 2:1 field matching scheme. The 1x field is a 44 X 22 mm rectangle that is symmetrically aligned to two 22 X 22 mm 5x reduction fields. Overlay measurements were collected at 33 sites per reduction field (or 66 sites per Ultratech field) and the resulting data was analyzed using a modified grid registration model that fully supports the 2:1 matching geometry. Two complementary optimization techniques were developed, the first of which assumes corrective action only on the 1x stepper. The more sophisticated approach supports corrective action on both the 1x and 5x reduction stepper. Next, both techniques were applied to the measured mix-and-match data with the results suggesting a specific set of corrective action that could be applied to the 1x and 5x reduction steppers. Based on these results, it was found that there is a substantial registration benefit to exerting simultaneous corrections on both stepper types as opposed to controlling each stepper individually.
Process simulation and modeling techniques have demonstrated significant success in predicting the behavior of optical lithography for semiconductor processes with photoresist thicknesses below 2 microns. An extension of these same principles and methods has been applied to thick resist process up to 10 microns. This study examines the use of simulation analysis in conjunction with experimental results to study the effects of photoresist film thickness and photoresist properties on lithographic performance. The simulation results examine various photoresist model parameters and their impact on typical lithographic process indicators such as depth of focus and exposure latitude. These results show the importance of the photoresist absorption parameter A (micrometers <SUP>-1</SUP>) and the developer selectivity n in determining lithographic performance. High values of n provide increased process latitude, while low values of A reduce the required exposure energy.
Wafer scale integration (WSI) lithography is the technique used to fabricate ultra large scale integration (ULSI) integrated circuits significantly greater in size than current products. Applications for WSI lithography include large solid state detector arrays, large area liquid crystal displays, high speed mainframe supercomputers, and large random access memories. The lithography technology required to manufacture these devices is particularly challenging, requiring stringent control of both submicron critical dimensions and accurate alignment of level to level device patterns over large chip areas.
A new generation i-line optical stepper utilizing the established benefits of the 1x Wynne- Dyson lens design has been developed for mix-and-match lithography. Based on the advantages of cost of ownership and high throughput capability, the Ultratech 2244i was specifically designed as a cost effective approach to complement high NA reduction steppers in a mix-and-match environment, especially for high volume DRAM and ASIC manufacturing. This system features an ultra-large image field of 22 X 44 mm with a 0.32 numerical aperture lens with an illumination bandwidth of 20 nanometers (355 to 375 nm). As a result, this system provides 0.8 micrometers manufacturing capability. These features provide improved critical dimension (CD) interference effects and superior depth-of-focus for the 2244i.
Two photoresists were selected for alignment characterization based on their dissimilar coating properties and observed differences on alignment capability. The materials are Dynachem OFPR-800 and Shipley System 8. Both photoresists were examined on two challenging alignment levels in a submicron CMOS process, a nitride level and a planarized second level metal. An Ultratech Stepper model 1500 which features a darkfield alignment system with a broadband green light for alignment signal detection was used for this project. Initially, statistically designed linear screening experiments were performed to examine six process factors for each photoresist: viscosity, spin acceleration, spin speed, spin time, softbake time, and softbake temperature. Using the results derived from the screening experiments, a more thorough examination of the statistically significant process factors was performed. A full quadratic experimental design was conducted to examine viscosity, spin speed, and spin time coating properties on alignment. This included a characterization of both intra and inter wafer alignment control and alignment process capability. Insight to the different alignment behavior is analyzed in terms of photoresist material properties and the physical nature of the alignment detection system.
The resolution and critical dimension control requirements for photomask fabrication are increasing at a dramatic rate due to advances in wafer lithography systems and photoresist technology. For example, phase shifting techniques for 5x reduction steppers require subresolution phase shifter elements as small as 0.5 micrometers to be patterned on the reticle. Unity magnification systems such as 1x optical steppers and deep UV 1x steppers require sub- half micron resolution on the reticle. The latest generation of electron-beam mask making systems is capable of patterning these structures in the resist film. However, traditional wet etch is not capable of successfully transferring the pattern from the resist into the chrome. This paper discusses a dry etch chrome process that has been developed at TRW. Sub-half micron resolution is characterized and explained in terms of chrome etching parameters. Selectivity and process sensitivities are explored for a potential manufacturing process. Finally, a dry etch process is used to fabricate actual reticles for an Ultratech 1500 1x optical stepper for use in a wafer manufacturing line.
Fabrication of integrated circuits at subhalf micron geometries is currently feasible only using advanced lithography technologies such as direct write e-beam and x-ray systems. These systems are extremely expensive and have low effective throughputs for a production environment. A mix-and-match approach using optical steppers for noncritical levels can dramatically increase productivity and control total lithography costs. A major impact for mix- and-match lithography is the total root mean squared alignment errors between systems. Implementation of a larger overlay budget to accommodate mix-and-match errors adversely impacts design rules for submicron technologies. However, a maskless lithography tool such as direct write e-beam offers the potential to compensate for systematic errors during wafer patterning and dramatically reduce the overlay budget for those layers. At TRW, a mix-and- match scheme has been developed between a Hitachi HL-700D e-beam direct write system and a Ultratech 1500 wide field 1X stepper. A previous analysis using only the linear distortion terms between these systems was found to be inadequate to fully explain the observed overlay. In this study, both linear and higher order distortion components are extracted using a large number of distributed measurement sites in the stepper field. These distortion terms are then analyzed to determine their source. Compensation techniques including both system hardware adjustments and e-beam software are investigated to enhance registration capabilities.
The requirements for mask fabrication have increased dramatically with recent advances in lithographic techniques and new i-line, x-ray and deep UV systems. For example, phase shifting masks for 5x steppers require submicron phase shifters, tight critical dimension control and pattern alignment capabilities. X-ray steppers and other lx technologies require subhalf micron resolution and even tighter critical dimension control with excellent dimensional linearity. These requirements approach the limit of capabilities of traditional e-beam mask fabrication systems.
At TRW, a Hitachi HL-700D direct write on wafer e-beam tool has been used in a production environment for a half micron CMOS technology. This shaped beam vector scan system is also capable of mask fabrication. It offers unique mask fabrication capabilities due to the implementation of advanced proximity correction algorithms to maintain submicron dimensional control and line size linearity. The system also supports a 0.10 micron x-barplus three sigma alignment capability.
This paper will review a program that has been implemented to evaluate the ultimate resolution and overlay capabilities of the Hitachi system for mask fabrication. Subhalf micron mask resolution will be characterized and explained in terms of proximity correction algorithms. Different chrome etching techniques will be evaluated for critical dimensional control. Finally, an analysis of the effectiveness of the alignment system for phase shifting masks will be presented using applicable test structures
This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.
Half-micron lithography for a production environment is not considered realistic with currently available lithography tools. While optical steppers have high wafer throughputs, they do not have sufficient process latitude at half-micron geometries. In contrast, advanced technologies with sufficient capabilities for half-micron processing such as direct-write e-beam and x-ray lithography are extremely expensive and have low effective throughputs. A mix-and- match lithography approach can take advantage of the best features of both types of systems by sing an optical stepper for noncritical levels and an advanced lithography system for critical levels. In order to facilitate processing of a triple level metal half-micron CMOS technology, a mix-and-match scheme has been developed between a Hitachi HL-700 D e-beam direct write system and an Ultratech 1500 wide-field 1x stepper. The Hitachi is used to pattern an accurate zero or registration level. All critical levels are exposed on the Hitachi and aligned back to this zero level. The Ultratech is used to align all other process levels which do not have critical targets that are placed on subsequent process levels. The mix-and-match approach is discussed, and optical to e-beam as well as e-beam to optical alignment results from seven production lots are presented. The linear alignment error components X translation, Y translation, rotation and magnification are extracted and analyzed to determine their source. It was found that a simple adjustment improved the registration capabilities of these two lithography tools by reducing the X translation, Y translation and rotation standard deviations by a factor of two or more, while greatly reducing the magnification errors between the two tools.
An evaluation of an optical lithography alignment target strategy based on a trench structure dry etched in a silicon substrate prior to device fabrication is presented. Use of this silicon trench target provides a robust target which is necessary for alignment of difficult layers on processes employing multilevel metallizations with planarizing dielectric films. In comparison the use of other targets schemes are less effective on steppers that utilize a darkfield alignment technique when aligning these difficult backend metal process layers. Additional motivation for this study is the requirement of tighter overlay specifications at all levels as device geometries are reduced to the submicron region. This silicon trench target scheme minimizes the total root mean square overlay budget by aligning all process layers to the silicon trench target. Therefore this technique can effectively enhance efforts to scale device dimensions. In this study the effects of target polarity target dimensions target design and silicon etch depth of the target on process alignment latitude are shown for a submicron CMOS process of three layers of metallizations with intermetal planarizing dielectric films. The selection of thin films deposited over the silicon trench target during the process sequence was also optimized to enhance the silicon trench target. The process alignment latitude results of this evaluation are based on an assessment of alignment target signal integrity including signal to noise ratio and target symmetry. In addition quantification