The availability of EUV lithography is the mainstream for resolving critical dimension of the advanced technology nodes, currently in the range of 18nm and below . The first insertion of EUVL into manufacturing utilizes chemically amplified resist (CAR) . The filtration of CAR, both at bulk and point-of-use (POU), has already demonstrated in ArF and ArF immersion lithography to play a significant role for microbridges reduction essentially by removing hard particle and gels [3-6]. With respect to ArFi, EUV is bringing new challenges not only for the achievement of the required line roughness, sensitivity and resolution, but also for the need of a substantial reduction of defects such as line collapse, microbridges and broken lines. In this study, it demonstrated the ability of utilizing novel POU filtration to modulate microbridges and achieving superior start-up behavior, both crucial for enabling EUVL at high volume manufacturing. Different POU filters were tested at the imec EUV cluster comprised of TEL CleanTrack LITHIUS Pro-Z and ASML NXE:3400B. The start-up performance, assessed by measuring defects down to 19nm size as a function of the flushing solvent volume, has shown the fast achievement of attaining a stable baseline. Lithography experiments targeting reduction of on-wafer defectivity, carried out with commercially available photoresists, have consistently shown a substantial reduction of after resist development (ADI) and after resist etch (AEI) microbridges on a 16nm L/S test vehicles. The effect of membrane physical intrinsic designs and novel cleaning of POU devices are discussed.
Currently, there are many developments in the field of advanced lithography that are helping to move it towards increased HVM feasibility1,2,3,4. Targeted improvements in hardware design for advanced lithography are of interest to our group specifically for HVM metrics such as LWR improvement, dose reduction processes, and defect density reduction. In this work we are building on our experience to improve LWR in an advanced lithographic process by employing novel hardware solutions on our SCREEN DUO coat develop track system5 . Our approach is to implement post-litho annealing to improve resist line roughness. Although it is preferable to achieve such improvements post-etch process we feel, as many do, that post-patterning improvements are a precursor to improvements after etching6 . We hereby present our work utilizing the SCREEN DUO coat develop track system to improve aggressive dense L/S patterns.