Extreme ultraviolet lithography (EUVL) uses a 13.5nm exposure wavelength, all-reflective projection optics, and a reflective mask under an oblique illumination with a chief ray angle of about 6 degrees to print device patterns. This imaging configuration leads to many challenges related to 3D mask topography. In order to accurately predict and correct these problems, it is important to use a 3D mask model in full-chip EUVL applications such as optical proximity correction (OPC) and verifications. In this work, a fast approximate 3D mask model developed previously for full-chip deep ultraviolet (DUV) applications is extended and greatly enhanced for EUV applications and its accuracy is evaluated against a rigorous 3D mask model.
As Extreme Ultraviolet Lithography (EUVL) enters the pre-production phase, the need to qualify the Electronic Design
Automation (EDA) infrastructure is pressing. In fact, it is clear that EUV will require optical proximity correction
(OPC), having its introduction shifted to more advanced technology nodes. The introduction of off-axis illumination will
enlarge the optical proximity effects, and EUV-specific effects such as flare and shadowing have to be fully integrated in
the correction flow and tested.
We have performed a model calibration exercise on the ASML NXE:3100 pre-production EUVL scanner using Brion's
Tachyon NXE EUV system. A model calibration mask has been designed, manufactured and characterized. The mask
has different flare levels, as well as model calibration structures through CDs and pitch. The flare modulation through
the mask is obtained by varying tiling densities. The generation of full-chip flare maps has been qualified against
experimental results. The model was set up and calibrated on an intermediate flare level, and validated in the full flare
Wafer data have been collected and were used as input for model calibration and validation. Two-dimensional structures
through CD and pitch were used for model calibration and verification. We discuss in detail the EUV model, and analyze
its various components, with particular emphasis to EUV-specific phenomena such as flare and shadowing.
EUVL requires the use of reflective optics including a reflective mask. The mask consists of an absorber layer pattern on
top of a reflecting multilayer, tuned for 13.53 nm. The EUVL mask is a complex optical element with many parameters
contributing the final wafer image quality. Specifically, the oblique incidence of light, in combination with the small
ratio of wavelength to mask topography, causes a number of effects which are unique to EUV, such as an HV CD offset.
These so-called shadowing effects can be corrected by means of OPC, but also need to be considered in the mask stack
In this paper we will present an overview of the mask contributors to imaging performance at the 27 nm node and below,
such as CD uniformity, multilayer and absorber stack composition, thickness and reflectivity. We will consider basic
OPC and resulting MEEF and contrast. These parameters will be reviewed in the context of real-life scanner parameters
both for the NXE:3100 and NXE:3300 system configurations.
The predictions will be compared to exposure results on NXE:3100 tools, with NA=0.25 for different masks. Using this
comparison we will extrapolate the predictions to NXE:3300, with NA=0.33.
Based on the lithographic investigation, expected requirements for EUV mask parameters will be proposed for 22 nm
node EUV lithography, to provide guidance for mask manufacturers to support the introduction of EUV High Volume
EUVL requires the use of reflective optics including a reflective mask. The mask contains a reflecting
multilayer, tuned for 13.5 nm light, and an absorber which defines the dark areas. The EUV mask itself is a
complex optical element with many more parameters than just the mask CD uniformity of the patterned
features that impact the final wafer CDU. One of these parameters is absorber height. It has been shown
that the oblique incidence of light in combination with the small wavelength compared to the mask
topography causes a so-called shadowing effect manifesting itself particularly in an HV wafer CD offset. It
was also shown that this effect can be essentially decreased by reducing absorber height and, in addition, it
can be corrected by means of OPC.
However, reduction of absorber height has a side effect that is an increased reflectivity of a mask black
border resulting in field-to-field stray light due to parasitic reflections. One of the solutions to this problem
is optical process correction (OPC) at field edges. In this paper we will show experimental data obtained on
ASML EUV Alpha tool illustrating the black border effect and will demonstrate that this effect can be
accurately predicted by Brion Tachyon EUV model allowing for a significant cross field CD uniformity
improvement with mask layout correction technique.
Also we show by means of rigorous 3D simulations that it is possible to improve the imaging performance
significantly by performing global optimization of mask absorber height and mask bias in order to increase
exposure latitude, decrease CD sensitivity to mask making variations such as CD mask error and absorber
stack height variations. By sacrificing some exposure latitude throughput of exposure tool can be increased
essentially and HV mask biasing can be reduced. For four masks with different absorber thicknesses from
44 nm to 87 nm it is proven experimentally by means of the EUV Alpha tool exposures of 27 nm L/S that
the absorber thickness can be tuned to maximize exposure latitude. It was also proven that dose to size
grows with absorber height and optimal feature bias depends on mask absorber height.
This paper investigates the application of source-mask optimization (SMO) techniques for 28 nm logic device and
beyond. We systematically study the impact of source and mask complexity on lithography performance. For the source,
we compare SMO results for the new programmable illuminator (ASML's FlexRay) and standard diffractive optical
elements (DOEs). For the mask, we compare different mask-complexity SMO results by enforcing the sub-resolution
assist feature (SRAF or scattering bar) configuration to be either rectangular or freeform style while varying the mask
manufacturing rule check (MRC) criteria. As a lithography performance metric, we evaluate the process windows and
MEEF with different source and mask complexity through different k<sub>1</sub> values. Mask manufacturability and mask writing
time are also examined. With the results, the cost effective approaches for logic device production are shown, based on
the balance between lithography performance and source/mask (OPC/SRAF) complexity.
The switch from 193i to EUV Photolithography will bring some fundamental changes in exposure. The flare levels of an
EUV machine are significantly higher compared with standard 193i machines. Moreover shadow effects on the reticle
are not equivalent to 193i. It is inevitable that these fundamentals require modifications in the Optical Proximity
Correction (OPC) flow.
In this paper in collaboration with ASML BRION the critical enabling steps of the Mask Data Preparation (MDP) for
EUVL, Flare, Shadowing and Optical and Process Corrections (OPC), are investigated.
We measured the needs of the EUV MDP flow against the capabilities of a state-of-the art OPC flow built for 193i.
Adaptations are being made to implement features which are currently not available in a 193i based flow.
We present a feasibility study of the Model Based approach to the EUV OPC on a wide selection of features. Also we
demonstrate simulations and verification of the EUV modeling capabilities of the TachyonTM with various levels and
ranges of flare and prove the applicability of the reviewed approach to the process development for the 27nm EUV
We also evaluated the accuracy of the EUV OPC modeling and expected OPC corrections on the reviewed selection of
clips as a substantial part of the overall CDU budget.
Finally an overall EUV OPC flow as a manufacturable solution based on the Tachyon's predictions and ASML's
knowledge of Photolithography was discussed.
Accurate modeling of EUV Lithography is a mandatory step in driving the technology towards its foreseen insertion
point for 22-16nm node patterning. The models are needed to correct EUV designs for imaging effects, and to
understand and improve the CD fingerprint of the exposure tools. With a full-field EUV ADT from ASML now
available in the IMEC cleanroom, wafer data can be collected to calibrate accurate models and check if the existing
modeling infrastructure can be extended to EUV lithography. As a first topic, we have measured the CD on wafer of a
typical OPC dataset at different flare levels and modeled the evolution of wafer CD through flare, reticle CD, and pitch
using Brion's Tachyon OPC engine. The modeling first requires the generation of a flare map using long-range kernels
to model the EUV specific long-range flare. The accuracy of the flare map can be established independently from the CD
measurements, by using the traditional disappearing pad test for flare determination (Kirk test). The flare map is then
used as background intensity in the calibration of the traditional optical models with short-range kernels. For a structure
set of 600 features and over a flare range of 4-6%, an rms fit value of 0.9nm was obtained.
As a second aspect of the modeling, we have calibrated a full resist model to process window data. The full resist model
is then used in a combination with experimental measurements of reticle CD, slit intensity uniformity, focal plane
behavior, and EUV thick mask effects to model the evolution of wafer CD across the exposure field. The modeled
evolution of CD across the exposure field was found to be a good match to the experimentally seen evolution of CD
across the field, and confirms that the 4 factors mentioned above are main contributions to the CD uniformity across the
field. As such the modeling work enables a better understanding of the errors contributing to CD variation across the
field for EUV technology.