Control on the order of a nanometer is crucial for present days advanced logic, SRAM, and DRAM integrated circuits (IC). This level of control is necessary to ensure proper functioning of these circuits. In logic and SRAM applications the most important control parameter is the critical dimension of the gate conductor and for DRAM deep trench it is the etch depth. Advanced Process Control (APC) using feedforward and feedback closed loop techniques have been implemented in fabs for over two decades. Up until recently most fabs have used standalone metrology tools exclusively to collect critical wafer parameters. In this paper, a fully integrated Transforma<sup>TM</sup> Closed Loop (CL) etch system is used to facilitate nanometer gate etch control by enabling, for the first time, real-time feedforward and feedback measurement on a gate etch process.
The extendibility of optical lithography using KrF and ArF exposure tools is still being investigated, even, being demanded strongly now, due to the unforeseen issues, high cost, and general difficulty of NGLs - including F<sub>2</sub> and immersion lithography. In spite of these challenges Moore's Law requires continued shrinks and the ITRS roadmap still keeps its aggressive timetable. In order to follow the ITRS roadmap, the resolution must keep improving by increasing the lens NA for optical exposure tools. However, the conventional limit of optical resolution (kpitch=0.5) is very close for the current technologies, perhaps limiting progress unless NGL becomes available quickly. Therefore we need to find a way to overcome this seemingly fundamental limit of optical resolution. In this paper, we propose two practical two-mask /double-exposure schemes for doubling resolution in future lithography. One method uses a Si-containing bi-layer resist, and the other method uses Applied Materials' APF (a removable hard mask). The basic ideas of both methods are similar: The first exposure forms 1:3 ratio L/S patterns in one resist/hard mask layer, then the second exposure images another 1:3 ratio L/S pattern in-between the two lines (or two spaces) formed by the first exposure. The combination of these two exposures can form, in theory, kpitch=0.25 patterns. In this paper, we will demonstrate 70nm L/S pattern (140nm pitch) or smaller by using a NA0.68 KrF Scanner and a strong-RET reticle, which corresponds to kpitch = 0.38 (k1=0.19). We will also investigate the critical alignment and CD control issues for these two-mask/dual-exposure schemes.
A PECVD deposited carbon hardmask is combined with dielectric anti-reflective coating (DARC) for the patterning of sub-90nm lines with 248nm lithography. Using this CVD dual layer stack, <1% reflectivity control is demonstrated for both 248nm and 193nm lithography. The film stack is tested with an etch integration scheme to reduce polysilicon gate critical dimension (CD). The dual layer stack can be defined with less than 100nm thick photoresist. Because of the minimal resist required to open the stack, this film stack enables an integration scheme that extends conventional photoresist trim processes up to 70% of the starting line width. In addition to conventional trim process, a resistless carbon mask trim process is investigated to further shrink the gate critical dimension. The results show that the carbon hardmask has greater than 6:1 etch selectivity to polysilicon, enabling the extension of the resist trimming technique to generate sub-30nm structures using 248nm lithography.
Process tolerances for critical dimensions are becoming increasingly severe as lithographic technology drives the minimum integrated-circuit feature size toward 0.1 micrometers and below. In response, Optical Critical Dimension metrology (OCD), an optical-wavelength light-diffraction technique, is currently undergoing an industry-wide evaluation as a fast, accurate, and non-destructive sub-100nm line-width monitor. As such, effective process monitoring requires detailed understanding of the correlation between CD-SEM and the OCD measurements. Correlation in CD measurements between the OCD technique and SEM techniques is investigated in this paper by measuring photo-resist gratings on a polysilicon gate film stack. Intra-grating CD variation is shown to account for scatter in the correlation plot. A positive offset in the correlation is also observed and a mechanism is proposed to account for the discrepancy. Correlation between CD-SEM and OCD is also demonstrated for samples with three different pitch sizes. A qualitative line-profile correlation between cross-section SEM (X-SEM) and OCD is presented for photoresist gratings in a Focus Exposure Matrix (FEM).