Semiconductor fabrication process defect inspection industry is always driven by inspection resolution and through-put. With fabrication technology node advances to 2X ~1Xnm range, critical macro defect size approaches to typical CMOS camera pixel size range, therefore single pixel defect detection technology becomes more and more essential, which is fundamentally constrained by camera performance. A new evaluation model is presented here to specifically describe the camera performance for semiconductor machine vision applications, especially targeting at low image contrast high speed applications. Current mainline cameras and high-end OEM cameras are evaluated with this model. Camera performances are clearly differentiated among CMOS technology generations and vendors, which will facilitate application driven camera selection and operation optimization. The new challenges for CMOS detectors are discussed for semiconductor inspection applications.
High speed strobe based illumination scheme is one of the most critical factors for high throughput semiconductor defect inspection applications. HB LEDs are always the first and best options for such applications due to numerous unique advantages such as excellent spatial and temporal stability, fast responding time, large and linear intensity dynamic range and no heat issue for the extremely low duty cycle applications. For some applications where a large area is required to be illuminated simultaneously, it remains a great challenge to efficiently package a large amount of HB-LEDs in a highly confined 3D space, to generate a seamless illuminated area with high luminance efficiency and spatial uniformity. A novel 3D structured collimation lens is presented in this paper. The non-circular edge shape reduces the intensity drop at the channel boundaries, while the secondary curvatures on the top of the collimator lens efficiently guides the light into desired angular space. The number of the edges and the radius of the top surface curvature are control parameters for the system level performance and the manufacture cost trade-off. The proposed 3D structured LED collimation lens also maintains the benefits of traditional LED collimation lens such as coupling efficiency and mold manufacture capability. The applications can be extended into other non-illumination area like parallelism measurement and solar panel concentrator etc.
Semiconductor see-through-silicon metrology and inspection applications use traditionally InGaAs based cameras due to
perfect spectral sensitivity. But InGaAs cameras do not carry equivalent advantages as Silicon based imagers such as
pixel size, pixel array resolution and through-put etc. This paper first reviews the novel technologies which dramatically
enhance silicon imagers' sensitivity for this see-through silicon application. Inspection through-put is analyzed based on
multiple system implementation:, start-stop scan mode vs. continuous scan mode, 2D cameras vs. TDI line scan cameras,
against to traditional InGaAs camera based continuous scan platform. The simulation data shows that systematic
through-put based on 2D silicon cameras can be competitive to today's InGaAs system, while TDI line scan system can
be much faster than system based on near future's high resolution and high speed InGaAs cameras.
Dark-field defect inspection is an essential quality control method for the semiconductor fabrication industry, and it is broadly applied for micro particles detection in almost every fabrication process. Diode laser based dark-field illumination systems (LDFs) play a critical role in such illumination schemes due to its unique optical/mechanical properties. This paper discusses a complete LDF system model, includes the mathematical and optical descriptions of LDF system fundamentals. A series of trade-off curves are developed in this model, which describe system performance under different constraints. This model can either efficiently facilitate system design work for generic/unique applications, or can be used to evaluate existing LDF system performance.
With semiconductor development processes hitting harder and harder on Moore's law to continuously scale down, high
density advanced packaging technologies become a promising alternate route to improve transistor density. Chip
integration IO/cm<sup>2</sup> density jumps quickly by orders from 2D packaging of 10<sup>2</sup> to wire bonded chip stack of 10<sup>3</sup>, to TSV
of 104~105 and to advanced 3D integration of 10<sup>5</sup> to 10<sup>6</sup>. Starting with wire bonding and now prevailing with TSV, more
and more silicon layers are stacked up in 3D dimension to improve system density. A typical stacked wafer sample has
two wafers glued together with patterned area sandwiched in between. Outer surfaces can be polished or unpolished bare
silicon surface, or patterned surface.
By utilizing diffractive, refractive and graded-index optics technology, a miniature (1 mm x 1 mm x 2 mm) Computer-Tomography Imaging Spectrometer (CTIS) sensor has been designed with 16 independent optical channels working in a snap-shot mode for hyper-spectral imaging. The designed prototype covers a 400~700 nm wavelength range. One optical channel has been fabricated and characterized. By azimuthally rotating this optical channel along the optical axis and collecting different dispersed images to simulate the full sensor read-out, the full hyperspectral detection scheme has been demonstrated.