Mr. Weicheng Hsu Profile

Weicheng Hsu

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Publications (2)

Proceedings Article | 16 March 2009 Paper

Advanced self-aligned double patterning development for sub-30-nm DRAM manufacturing

Weicheng Shiu, Hung Jen Liu, Jan Shiun Wu, Tsu-Li Tseng, Chun Te Liao, Chien Mao Liao, Jerry Liu, Troy Wang

Proceedings Volume 7274, 72740E (2009) https://doi.org/10.1117/12.813986

KEYWORDS: Double patterning technology, Optical alignment, Line edge roughness, Optical lithography, Scanners, Lithography, Extreme ultraviolet, Semiconducting wafers, Etching, Overlay metrology

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Although the Numerical Aperture (NA) has been greatly improved from 0.93 (dry) to 1.35 (wet) by the introduction of modern water immersion 193nm scanner since 2001, the realistic single exposure photolithography printing for mass production is still limited to ~40nm, even with the help of a variety of Resolution Enhancement Techniques (RETs). Theoretically, the 193nm immersion scanner with high index fluid or Extreme UV (EUV) scanner with a significantly shorter wavelength of 13.5nm would be the logical successors to water immersion 193nm scanner. However, considering tremendous technical difficulties to work with high index fluids and relatively immature and very low productivity of EUV at the moment, it's likely that both candidates have little chance to entering production prior to 2012. Additionally, the production schedule can be further pushed out due to formidable initial investment for the costly equipment and consumables associated with EUV given the present worldwide economic recession. Nano-imprint may be attractive for its low cost and versatile nature, however, long-term stability and logistics under production stress yet to be established. The hope to continue the thrust of Moore's Law into the sub-40nm regime before EUV era heavily counts on the success of the so-called Double Patterning Techniques (DPT). A variety of integration schemes have been developed or are still under development to harness the full capacity of DPT. Among them the spacer double patterning approach stands out because of the self-aligned characteristics and a cumulative great deal of experience on the handling of the spacer-related processes in traditional CMOS process integration. The final goal of most research works around Self-Aligned Double Patterning (SADP) focuses on achieving minimal added cost and high quality printing at the same time. However, most of the time the quality and the cost are compromised by applying non-production proven new material/new hardware and/or fancy integration approaches. In our study we purposely apply a more "classical" and relatively conservative integration scheme, with all unit process steps long proven in previous volume production. By carefully optimizing the relative CMP, films deposition, etch and cleaning processes, we are able to demonstrate 30nm line/space patterns by an NA 0.93 dry 193nm scanner with optimal CDU better than 3nm and high frequency line edge roughness (LER) close to 2nm/side. Additionally, by analyzing wafer quality for alignment and alignment residual in various alignment & overlay mark designs, projected residual overlay as little as 4nm can be readily obtained.

Proceedings Article | 4 December 2008 Paper

Spacer double patterning technique for sub-40nm DRAM manufacturing process development

Weicheng Shiu, William Ma, Hong Wen Lee, Jan Shiun Wu, Yi Min Tseng, Kevin Tsai, Chun Te Liao, Aaron Wang, Alan Yau, Yi Ren Lin, Yu Lung Chen, Troy Wang, Wen Bin Wu, Chiang Lin Shih

Proceedings Volume 7140, 71403Y (2008) https://doi.org/10.1117/12.804641

KEYWORDS: Double patterning technology, Etching, Lithography, Photomasks, Scanners, Critical dimension metrology, Line edge roughness, Semiconducting wafers, Optical lithography, Image processing

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