Although the Numerical Aperture (NA) has been greatly improved from 0.93 (dry) to 1.35 (wet) by the introduction of
modern water immersion 193nm scanner since 2001, the realistic single exposure photolithography printing for mass
production is still limited to ~40nm, even with the help of a variety of Resolution Enhancement Techniques (RETs).
Theoretically, the 193nm immersion scanner with high index fluid or Extreme UV (EUV) scanner with a significantly
shorter wavelength of 13.5nm would be the logical successors to water immersion 193nm scanner. However, considering
tremendous technical difficulties to work with high index fluids and relatively immature and very low productivity of
EUV at the moment, it's likely that both candidates have little chance to entering production prior to 2012. Additionally,
the production schedule can be further pushed out due to formidable initial investment for the costly equipment and
consumables associated with EUV given the present worldwide economic recession. Nano-imprint may be attractive for
its low cost and versatile nature, however, long-term stability and logistics under production stress yet to be established.
The hope to continue the thrust of Moore's Law into the sub-40nm regime before EUV era heavily counts on the success
of the so-called Double Patterning Techniques (DPT).
A variety of integration schemes have been developed or are still under development to harness the full capacity of DPT.
Among them the spacer double patterning approach stands out because of the self-aligned characteristics and a
cumulative great deal of experience on the handling of the spacer-related processes in traditional CMOS process
integration. The final goal of most research works around Self-Aligned Double Patterning (SADP) focuses on achieving
minimal added cost and high quality printing at the same time. However, most of the time the quality and the cost are
compromised by applying non-production proven new material/new hardware and/or fancy integration approaches. In
our study we purposely apply a more "classical" and relatively conservative integration scheme, with all unit process
steps long proven in previous volume production. By carefully optimizing the relative CMP, films deposition, etch and
cleaning processes, we are able to demonstrate 30nm line/space patterns by an NA 0.93 dry 193nm scanner with optimal
CDU better than 3nm and high frequency line edge roughness (LER) close to 2nm/side. Additionally, by analyzing
wafer quality for alignment and alignment residual in various alignment & overlay mark designs, projected residual
overlay as little as 4nm can be readily obtained.
Pursuit of lower k<sub>1</sub> for pushing the resolution limit becomes one of the most demanding tasks to meet stringent
patterning requirements in next generation lithography. Particularly, the patterning of densely packed array devices with
periodic and symmetric features is among the most challenging missions to enable high density memory chips to quickly
move forward as projected by Moore's Law. As dictated by the physical limitation of optical system design, current
immersion scanners are not capable of reliably printing feature sizes down to sub-40nm regime unless resorting to high
index fluids or other effective Resolution Enhancement Techniques (RETs). Fortunately, recent prosperous progress in
double patterning technique seems to give realistic hope as a straightforward bridge between the current immersion
scanners  and the relatively immature EUV scanners . State-of-the-art double patterning technique  includes the
well known LLE (Litho-Litho-Etch) , LELE (Litho-Etch-Litho-Etch) , self-aligned  and other approaches .
Among them the self-aligned approach is regarded as more appropriated for mass production of high density arrays due
to less concerned of overlay budget . In this paper, we studied the integrated lithography performance of one
innovative self-aligned double patterning scheme for the demonstration of sub-40nm capability by the use of the most
advanced 193nm dry scanner. In addition, silicon containing bottom reflective coating (BARC) was employed for the
CD trimming in order to optimize the lithography & etch process windows . A 37.5nm half-pitch L/S memory array
with well controlled line edge roughness (LER) was successfully demonstrated in this work by the above mentioned selfaligned
spacer approach. The equivalent k<sub>1</sub>~0.146 was readily achieved without too much complex integration, which is
especially suitable for the future high density memory arrays as in FLASH or DRAM.