Optical network-on-chips (ONoCs) will play an important role for optical interconnects in the next generation chip multiprocessors (CMPs). Recent advances in silicon integrated photonics make it viable to develop ONoCs using the
standard CMOS process. This paper will introduce our work on cascaded-multiring-based tunable filters and ring-based integrated switchable wavelength routers.
RISC and DSP, two main architectures, have their own features. The main idea of RISC is “simple is fast”. Acting as controller, RISC is based on Load/Store structure, register-register Instruction Set Architecture (ISA), general purpose registers and cache. On the other hand, designed for signal processing, DSP emphasizes large data accessing and fast computing. It’s based on register-memory ISA, diverse addressing modes, data address generator, multiplier accumulator and RAM. As Embedded Systems grow fast, no single core architecture, neither RISC nor DSP, could meet the needs anymore. Combination is necessary. There are two kinds of combination: dual-core or single core. Single core means RISC core and DSP core melt into one core with common resource and unified ISA. A 32b media processor named MediaDSP3201 (MD32 for short) is a new member of this family. In this paper, the MD32 design is introduced and concentrated on ISA design and pipeline design. They are important in architecture design. Compatibility runs through the whole design. The ISA should include features from both RISC ISA and DSP ISA. The pipeline should fit the designed ISA as good as possible. MD32 was made by TSMC at the first try on 2004 spring. Application programs running on it show that the design is successfully and the chip is suitable for Embedded System applications.
With the pressure from the design productivity and various special applications, original design method for DSP can no longer keep up with the required speed. A novel design method is needed urgently. Intellectual Property (IP) reusing is a tendency for DSP design, but simple plug-and-play IP cores approaches almost never work. Therefore, appropriate control strategies are needed to connect all the IP cores used and coordinate the whole DSP. This paper presents a new DSP design procedure, which refers to System-on-a-chip, and later introduces a novel control strategy named DWC to implement the DSP based on IP cores. The most important part of this novel control strategy, pipeline control unit (PCU), is given in detail. Because a great number of data hazards occur in most computation-intensive scientific application, a new effective algorithm of checking data hazards is employed in PCU. Following this strategy, the design of a general or special purposed DSP can be finished in shorter time, and the DSP has a potency to improve performance with little modification on basic function units. This DWC strategy has been implement in a 16-bit fixed-pointed DSP successfully.
Proc. SPIE. 5309, Embedded Processors for Multimedia and Communications
KEYWORDS: Human-machine interfaces, Digital signal processing, Wavelets, Field programmable gate arrays, Computer simulations, Telecommunications, Signal processing, Software development, Multimedia, Data communications
Hardware/software co-simulation is a key step in hardware/software co-design flow. In this paper, a reconfigurable co-simulation platform called MPSP for media processor is described. This platform can be configured on both hardware and software quickly to accommodate different media processor for different simulation specification. The design of co-simulation environment on MPSP is based on library. A reconfigurable IP library and a software pack with API interface are provided as a part of MPSP. Based on this platform, the FPGA based co-simulation processing is greatly accelerated.
The prediction error can be decreased by incorporating with high accuracy estimation and compensation, and the performance of compressed video can be improved. Two fast algorithms of fractional-pixel accuracy video motion estimation are proposed in this paper. After half-pixel accuracy motion estimation, a high accuracy motion estimation can be calculated with the intermediate results. The algorithm is based on the intermediate results in half pixel accuracy motion estimation, and traditional fast block matching algorithms can also be implemented in half pixel accuracy. The arbitrary fractional-pixel accuracy motion estimation can be achieved directly, at the cost of small computational overhead. The approach described in this paper eliminates the systematic limitations of conventional block matching. Experimental results using typical video sequences show that the proposed algorithm can achieve better PSNR and lower bit rates in higher fractional pixel accuracy than in the half pixel motion estimation and compensation. These fast motion estimation algorithms provide methods for studying higher pixel accuracy motion estimation in video compression coding. The proper fractional pixel accuracy motion estimation and compensation by truncating the precise results will be the best way to achieve more efficiently video compensation and higher image quality.