A study of a silicon metal oxide semiconductor (MOS)-type light-emitting device (LED) in which the p–n junction works under a reverse bias and the gate voltage is applied to modulate the electric field distribution from the p+ region through the n region. The use of gate voltage could result in the generation of a field-induced junction which leads to a decrease of the operating voltage of the LED compared to the two terminal p–n junction LED. The dynamics of the photonic emission in the structure and its related response time, and then a more detailed theoretical and simulation understanding of the photonic emission is achieved, which definitively demonstrates the capability of the device in which a reverse-bias region showing light modulation with multi-GHz bandwidth and gigabit-per-second data rate at near-infrared wavelength. Although the emitted optical power is weak, it is advantageous to utilize the device in all-silicon optoelectronic integrated circuits, especially for short-distance on-chip optical interconnects achieved by standard complementary MOS technology.
A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.
In 3D imaging application, large scale of SPAD arrays, low power consumption, compact and high accuracy quenching
circuit is necessary. In this paper we developed a simple and fast pulse sensing circuit with negligible static power
dissipation, and the afterpulsing effects are also significantly reduced by fast quenching process. The gated mode is used
and it can precisely set the turn-off time of each frame. Ensure SPAD is more reliable. Compare to other active
quenching circuits (AQC) for SPADs, the proposed circuit is ultra fast in signal pulse sensing and accurate in time
resolution with a low threshold, and it can be easily utilized in SPAD-array detectors for photon-flight-time measurement
with sub-nanosecond precision. The quenching circuit implemented by CSMC 0.5-μm CMOS technology is optimal
designed by using SPICE simulator, where an accurate SPICE model we established for InGaAs SPAD is embedded. The
simulation result shows that the proposed AQC can operate properly in all the static and transient states, and the rising
time of the sensed voltage pulse can be caught in 1ns, and its quenching time is less than 5ns. This is much suitable for
picosecond precision infrared sensing system.
In this paper, a complete SPICE model for single photon avalanche diode (SPAD) is
presented, which can be implemented into the Spectre simulation environment in cadence to
precisely simulate both static characteristic and the photon detection process. We show how
to build the static current model including the forward region, the dynamic junction
capacitance model, and the neutral zone resistor model. In addition, an avalanche pulse
detection system is established to verify the validity of the SPICE model. The simulated
avalanche pulse voltage waveforms show good consistency with the experimented ones.
A high performance, 128×128 pixel, snapshot Readout Integrated Circuit (ROIC) for IRFPA has been fabricated with
0.5μm Double Poly Double Metal (DPDM) n-well CMOS process. The pixel cell circuit uses an improved direct
injection structure with only four transistors to maintain large enough integration capacitror. One pixel cell occupies an
area of 50×50μm<sup>2</sup>. Each row's pixel signals are readout to the column amplifiers row by row in parallel, while the
column amplifiers are reset after each row's pixel signals are readout. The whole pixel cells are reset wholly after a frame
signals are all readout. The ROIC structure also provides dynamic image transpositionxinyuanjing xinyuanjing xi
(Invert, Revert) function to support a wide range of system requirements. It still has a build-in temperature sensor to
detect the temperature of the chip. The measurement results show that the readout chip works well at both room
temperature and 77K with 5V supply voltage. The fabricated chip has a maximum charge storage capacity of 6.48×10<sup>7</sup>
electrons and the active power dissipation of about 10mW. The proposed CMOS ROIC structure has been applied to