The incident surface power density in Massive Electron-beam Direct Write (MEBDW) during exposure is ~105 W/cm2, much higher than ~8 W/cm2 ArF scanners and 2.4 W/cm2 EUV. In addition, the wafer’s exposure in vacuum environment makes energy dissipation even harder. This thermal effect can cause mechanical distortion of the wafer during exposure and have has a direct influence on pattern placement error and image blur. In this paper, the thermo mechanical distortions caused by wafer heating for MEB system of different electron acceleration voltages have been simulated with finite element method (FEM). The global thermal effect affected by the friction force between the wafer and the wafer chuck as well as different thermal conductivities of the chuck material are simulated. Furthermore, the thermal effects of different lithography systems such as EUV scanners and conventional optical scanners are compared. The thermal effects of MEBDW systems are shown to be acceptable.
Reflective electron-beam lithography (REBL) employs a novel device to impress pattern information on an electron
beam. This device, the digital pattern generator (DPG), is an array of small electron reflectors, in which the reflectance
of each mirror is controlled by underlying CMOS circuitry. When illuminated by a beam of low-energy electrons, the
DPG is effectively a programmable electron-luminous image source. By switching the mirror drive circuits
appropriately, the DPG can ‘scroll’ the image of an integrated circuit pattern across its surface; and the moving electron
image, suitably demagnified, can be used to expose the resist-coated surface of a wafer or mask. This concept was first
realized in a device suitable for 45 nm lithography demonstrations. A next-generation device has been designed and is
presently nearing completion. The new version includes several advances intended to make it more suitable for
application in commercial lithography systems. We will discuss the innovations and compromises in the design of this
next-generation device. For application in commercially-practical maskless lithography at upcoming device nodes, still
more advances will be needed. Some of the directions in which this technology can be extended will be described.
Proc. SPIE. 8323, Alternative Lithographic Technologies IV
KEYWORDS: Lithography, Electron beam lithography, Electron beams, Silicon, Reflectivity, Electroluminescence, Monte Carlo methods, Computer aided design, Semiconducting wafers, Direct write lithography
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 16 nm technology node
and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) targeting high-volume 16 nm
half pitch (HP) production. This paper reviews progress in the development of the REBL system towards its goal of 100
wph throughput for High Volume Manufacturing (HVM) at the 2X and 1X nm nodes. We will demonstrate the ability to
print TSMC test patterns with the integrated system in photoresist on silicon wafers at 45 nm resolution. Additionally,
we present simulation and experimental results that demonstrate that the system meets performance targets for a typical
foundry product mix.
Previously, KLA-Tencor reported on the development of a REBL tool for maskless lithography at and below the 16 nm
HP technology node1. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards
developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam
direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been
used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 16 nm HP technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVM.
Massively E-beam maskless lithography (MEBML2) is one of the potential solutions for 32-nm half-pitch and
beyond. In the past, its relatively low throughput restricted EBDW development to mostly mask making, small volume
wafer production and prototyping. Recently the production worthy ML2 approaches, >10,000 e-beams writing in
parallel, have been proposed by MAPPER, KLA and IMS. These approaches use raster scan in pattern writing. Hence
the bitmap is certainly the final data format.
The bitmap format used to have huge data volume with fine pixel size to maintain the CD accuracy after electron
proximity correction (EPC). Data handling becomes necessary, especially on data transmission rate. The aggregated data
transmission rate would be up to 1963 Tera bits per second (bps) for a 10 WPH tool using 1-nm pixel size and 1-bit gray
level. It needs 19,630 fibers each transmitting 10 Gbps. The data rate per beam would be >20 Gbps in 10,000-beam
MEBML2. Hence data reduction using bigger pixel size to achieve sub-nm EPC accuracy is crucial for reducing the fiber
number to the beam number.
In this paper, the writing-error-enhanced-factor to quantitatively characterize the impact of CD accuracy by various
total blur in resist is reported; and we propose the vernier pattern to verify sub-nm CD accuracy and the in-house
dithering raster method to achieve sub-0.2-nm CD accuracy using multiple-nm pixel sizes, which could reduce the need
of the aggregated data rate to 11%, 33%, 44% and 79% of 1963 Tbps on 22-nm, 16-nm, 11-nm, 8-nm node respectively.
E-beam direct write (EBDW) is one of the potential solutions for technology nodes of 28-nm half-pitch (HP) and
beyond. Throughput limitation confined its development mostly to small-volume prototyping. Recently, proposals have been
made to achieve throughput greater than 10 wafers per hour (WPH) on a single column with >10,000 beams writing in
parallel (MEBDW), or even greater than 100 WPH by further clustering multiple columns within a typical production-tool
footprint. The MAPPER concept contains a CMOS-MEMS blanker array driven by high-speed optical data path architecture to simultaneously control >10,000 beams, switching them on and off independently.
The MAPPER Pre-Alpha Tool with a 110-beam, 5-keV column and a 300-mm wafer stage has been installed in a semiconductor manufacturing cleanroom environment and is ready for imaging test. In this paper, the resist imaging results
of 110-beam parallel raster-scan writing for 30-nm half-pitch (HP) dense hole on 300-mm wafer is shown. The challenges of
implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including resolution, local variation, focusing, energy latitude, proximity effect correction and electron scattering model fitting of hole patterning are discussed. Similar to mask-error-enhanced-factor (MEEF), the new writing-error-enhanced-factor (WEEF) to describe the impact of writing error, is introduced.
E-beam maskless lithography is a potential solution for 32-nm half-pitch (HP) node and beyond. The major concern
to implement it for mass production is whether its throughput can reach a production-worthy level. Without violating the
law of physics using unrealistic e-beam current, parallelisms in the writing beams and the data path are a few possible
solutions to achieve such high productivity. It has been proposed to realize throughput greater than 10 wafers per hour
(WPH) from a single column with >10,000 e-beams writing in parallel, or even greater than 100 WPH by further
clustering multiple columns within an acceptable tool footprint. The MAPPER concept contains a CMOS-MEMS
blanker array supported by high-speed optical data-path architecture to simultaneously control this high number of
beams, switching them on and off independently.
The MAPPER pre-α tool with a 110-beam 5-keV column and a 300-mm wafer stage has been built and is ready for
imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 32-nm logic circuit
layout on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2)
in mass production environment, including illumination, focusing, and CD uniformity, are discussed.
As the geometry of semiconductor devices continue to scale down, high-NA imaging will be used to enhance the resolution. Sub-resolution assistant features are used to gain depth of focus at the wafer. One of the challenges in patterning small assistant features during mask fabricating is resist collapse. Reducing resist thickness is one of the solutions. This necessitates an increase in the selectivity of chromium (Cr) to photo-resist (PR). The selectivity determines the PR remaining on the mask after Cr etching. Insufficient remaining PR will induce pinhole-type clear defect and poor line edge roughness (LER). In this paper, the Cr-to-PR selectivity was studied under induced couple plasma (ICP) and quasi-remote plasma environment. PR remaining, etching bias, and critical dimension uniformity (CDU) are the main subjects for evaluation. To understand the etching behavior for higher selectivity, design of experiment (DOE) L4 by Taguchi method is used to find the dominating factors. By adopting the optimized etching recipe, the resist can be thinned down to effectively improve its collapse margin, especially for smaller assistant features. The results show that 72-nm assistant features on mask can be patterned for early 32-nm node development. This paper also suggests several approaches that can be used to reduce the required resist thickness, such as hard-mask, film thickness reduction, and etcher hardware modification.
The control of global critical dimension uniformity (GCDU) across the entire mask becomes an important factor for the high-end masks quality. Three major proceses induce GCDU error before after-developing inspection (ADI) including the E-Beam writing, baking, and developing processes. Due to the charging effect, the fogging effect, the vacuum effect and other not-well-known effects, the E-Beam writing process suffers from some consistent GCDU errors. Specifically, the chemical amplified resist (CAR) induces the GCDU error from improper baking. This phenomenon becomes worse with negative CARs. The developing process is also a source of the GCDU error usually appears radially. This paper reports the results of the study of the impact of the global CD uniformity on mask to wafer images. It also proposes solutions to achieve better masks.
In this paper, a quantitative evaluation of mask quality in the domain of 2D pattern fidelity and a method of assessing the OPC model effectiveness are investigated. The spirit of our algorithm is to characterize the wafer lithographic performances of both the real physical mask and the ideal OPCed layout mask that the physical mask is based on. To acquire these performances, we adopted a CD-SEM image process technique for transforming an actual SEM mask image into a simulation-friendly format like GDSII together with the methods to correctly handle the image transformation and interpret the simulation results. Finally, the images, such as the simulated aerial images, the simulated or observed resist top views, are superposed for comparison using logic operation.
Nowadays, the CD (Critical Dimension) control on masks manufacturing plays an important role in photolithography process for 90-nm node technology and below. The process performance of photolithography
will degrade severely even when the mask CD error is small. One of the most important process-induced mask CD errors comes from the dry etching process. With the loading effect due to environment pattern variations, isolated and dense patterns have different etching biases. Furthermore, the loading effect can induce an overall
CD variation called global loading effect contributed from the pattern density change in large areas and a CD variation on individual monitor pattern called micro-loading effect contributed from various feature dimensions in the near region. The micro-loading effect can also be classified as the “nearest spacing” effect which is dependent upon the space between the nearest neighbor pattern and the monitor pattern, and the “nearest
neighbor” effect which is dependent upon the size of the nearest neighbor feature around the monitor pattern. All of these effects enlarge the total range of mask CD linearity and proximity errors.
In this paper we report the result of the global loading effect and micro-loading effect by varying pattern densities and feature dimensions nearby. With the design of test pattern, the global loading effect and the micro-loading effect can be separated. The CD variation dominated by the micro-loading effect in the dry etching process is observed. This large etching bias change resulted from the micro-loading effect is consistent with the depletion of radical species in the narrow space during the etching process.