In recent years, the gain cell based eDRAM has got more and more interest for high density and logic-compatible embedded memories. It is widely used in image processing and biomedical applications as it can work as a dual-port memory with a small area. A hidden refresh scheme is proposed for the dual-port gain cell eDRAM to avoid the conflict between accesses and internal refreshes and to increase the data efficiency. By dividing the read, write and refresh operations into several stages, a hidden refresh controller controls to perform the dual-port access and internal refresh in parallel without any conflict. The hidden refresh scheme is integrated into a dual-port gain cell eDRAM of 256X256 in SMIC 130nm logic process. Simulation results demonstrate that the external accesses are performed without delay and dual-port data availability can reach 100%. And the access cycle time is only increased by about 10.9% compared with traditional distribution refresh method. The refresh power of the eDRAM is about 60μW/Mbit at 85°C.