Optical network on chip (ONoC) is an emerging paradigm for multi-core processor system for providing high bandwidth and low power consumption. The scalability of the multi-core processor system is limited by process yield and power density of the single chip. Multi-chip ONoC, which aggregate several smaller chips together, is proposed to overcome this problem. Nesting Ring Optical Network on Chip (NRO) is a multi-chip architecture, which has good performance in terms of throughput and delay. When the NRO scales to a large size ONoC architecture, it may suffer from severe congestion. We propose a novel resource reservation scheme for NRO to alleviate this problem. The resource reservation includes resource planning strategy and a Resource Allocation strategy. With our observation, lots of contentions occur in intersection nodes due to the lack of resource, because intersection nodes have heavier traffic than normal nodes. The proposed resource planning strategy can offer more optical resource for intersection nodes specifically, and keep the original number of wavelengths in the normal nodes, which maintains good power efficiency of NRO. Additionally, unreasonable resource allocation method will lead to contentions. We employ backward resource reservation method in NRO architecture to avoid contentions in intermediate nodes of the path. The simulation results show that the proposed resource reservation scheme can reduce 85% blocking rate and 12% ETE delay compared with convention scheme at an injection rate of 0.4.
Optical network on chip (ONoC) is an attractive solution for multicore/many-core processor systems due to its high power efficiency and enormous bandwidth. However, as increasing numbers of cores need to be interconnected, the scalability of a many-core processor on a single chip is limited by its process yield and power density. A multichip architecture is, therefore, proposed to improve the scalability of ONoC. In multichip architectures, the throughput and traffic delay rely on both the intrachip and interchip networks. To exploit the advantages of multichip systems, first we propose a multichip ONoC architecture for a many-core processor system that employs a nesting ring topology. The design principles of multichip systems of different sizes are then investigated to achieve higher throughput and lower delay. These principles include the number of chips and the number of cores per chip, which are considered jointly for the first time. Finally, we evaluate the performance of the proposed architecture, implemented in 240-core and 400-core systems, respectively, and compare it to two other traditional ONoC architectures with respect to throughput and end-to-end (ETE) delay. The results show that the proposed multichip system exhibits good scalability, achieves high throughput, and provides low ETE delay.