EUV lithography has enabled shrinking feature sizes up until iN7 using the current Ta-based mask absorber. As we explore next generation nodes, iN5 and beyond, the mask three dimensional (M3D) effects will have a significant impact at wafer level due to the mask architecture, and the oblique illumination angles [1-2]. In order to mitigate these effects, we explore the optical performance of two alternative mask absorber candidates; a High-k absorber and an attenuated phase shifting mask absorber (AttPSM) and compare them to the current Ta-based mask absorber. We evaluate and compare the mask absorbers for memory and logic layers by lithographic source-mask optimization (SMO) using Mentor’s pxSMO tool with ASML’s NXE3400B settings. For memory, contact-holes are simulated using dark-field mask whereas the pillars case is simulated with bright field mask to evaluate bright field as a mask option for EUV with alternative mask absorbers. For logic case, we test these absorbers on iN5 self-aligned block (SAB) layer . The self-aligned block layer is also simulated by adding sub-resolution assist features (SRAFs) to predict the insertion point of SRAFs for logic designs and see if new mask absorber material can reduce the need of SRAF insertion. SMO for memory case shows higher common depth of focus (cDOF) and lower edge placement error (EPE) for High-k absorber over the conventional TaBN mask absorber, whereas significant gain in normalized image log slope (NILS) is observed for the AttPSM absorber. The logic case also has better performance in terms of common depth of focus (cDOF), NILS, EPE mask error enhancement factor (MEEF) and process variation band (PV-band). Adding SRAF’s to iN5 SAB improves the PV-band and image shift through focus for all three cases.
With the advent of Multi-beam mask writers, curvilinear shapes are being realized with comparable metrics to Manhattan shapes when it comes to write times which has been the main issue with conventional VSB mask writers. Techniques like PLDC also enhance Multibeam writing of complex curvilinear patterns.
In the past Standard Cell (SDC) design was done with a gear ratio (polypitch/m1pitch) of 1:1. This inadvertently results in congestion on lower layers namely M1 as we try to push the design density. This can be improved by going to a gear ratio of 2/3 by which we derive additional M1 tracks (3 M1 tracks for every 2 poly) but the benefit derived out of a 2/3 gear ratio cell somewhat gets negated with the need for M2 in standard cells where MINT layer doesn’t fully cover M1. To resolve the problem with higher M2 usage in standard cells we can introduce 1.5D or curvilinear routing to make the final/minor routing connections. Here we try to present a study of different challenges and opportunities that arises as a result of introducing curvilinear routing in Standard cells (SDC).
In IN5 technology node when we go for a gear ratio (CPP/M1Pitch) of 2/3 we observe that for every standard cell we will need two variants of the cell. These two variants have M1 which are interleaved and shifted. We can live with only one variant of the cell but this inadvertently leaves gaps in between standard cells as the M1 grids will not align when they are abutted. Further study of the impact of the need of two variants reveals that in some standard cells (~9% in IN5) we end up with using M2 for completing the connections. This has many drawbacks (extra routing resources, congestion on M2, increase in area and reduced performance) which negates the benefit derived with 2/3 gear ratio.
To fix this problem we have two options. One is to use 1.5D routing and the other to use curvilinear routing. With this approach all the benefits of 2/3 gear ratio can be preserved (improved routing density, area and performance) without the need for M2.
A design implementation of the same in IN5 AO22D2 standard cell with CPP of 45nm and M1 pitch of 30nm has been done and the M2 routing (with default approach) has been eliminated. Although this approach has numerous benefits and extended applications (in signal routing) it does present significant challenges when it comes to EDA tools, verification, mask and OPC. We are in the process of evaluating different test cases for design, mask and OPC challenges with curvilinear routing in IN5 SDC. On the design front the challenges include library characterization, PPA and runtime analysis, RC extraction and design verification. On the mask and OPC front some of the challenges include regular versus ILT OPC and their process window comparison, understand the SRAF’s required, mask data volume and MRC.
A comprehensive understanding of the challenges and resolution of the same will entail a new scaling paradigm for standard cell designs and also enhance signal routing which in turn has numerous benefits when it comes to PPA.
In this work we are introducing a manufacturing flow for the SALELE Process in details. Starting with layout decomposition, where the drawn layer is decomposed into 4 Masks: 2 Metal-like Masks, and 2 Block-like Masks. Then each of these masks is subjected to Optical Proximity Correction (OPC) process, and here we explain more about the OPC recipe development for each mask. Then we introduce a verification flow that performs two levels of verifications: (a) Litho verification, where the litho fidelity of each mask is quantified based on image quality measurements. (b) Final Manufactured shapes verification vs. expected output. This work has been carried out on an N3 candidate layout designed by IMEC.
The current industry standard tantalum-based mask absorber (60 nm TaBN) gives strong 3D electromagnetic field (EMF) effects at wafer level, such as shadowing and pitch-dependent best focus shifts. A thinner mask absorber with higher EUV extinction coefficient or a phase shifting mask can mitigate 3D EMF effects . The alternative mask absorber materials would enable further downscaling to foundry 5nm node using state-of-the-art EUV scanners (with 0.33 numerical aperture “NA”) and facilitate future high NA imaging using single exposure. Here we evaluate insertion options on the patterning roadmap for alternative EUV mask absorbers, including high-k absorbers and attenuated phase shifting masks (attPSM) [1-2]. All studies are using relevant designs from foundry N5 logic node. Two alternative mask candidates are compared with the standard TaBN mask. We bring theoretical proof of concept that alternative mask absorber materials generate significant imaging gain in terms of established success criteria. On a set of predefined types of clips (with variations of 1D/2D, horizontal/vertical, dense/isolated patterns), we seek for higher depth of focus (DoF), higher image log slope (ILS), high illumination efficiency (ideally it would be equal to 1), lower pattern shift through focus (i.e., lower tele-centricity errors), lower mask error enhancement factor (MEEF). Source mask optimization (SMO) on N5 logic clip shows a more balanced source and larger common process window for high-k absorber over Ta-based absorber. Using the optical proximity correction (OPC) engine with high-k mask absorber, shows significant gain on overlapping process window (PW), process variation (PV) band, and less line end shortening. Applying advanced Resolution Enhancement Techniques (RET), sub-resolution assist features (SRAFs) on N5 designs demonstrated an improved process in terms of common depth of focus (cDoF), and image shift through focus. It was also observed that the process not using SRAFs with the high-k absorber had superior process window and image shift compared to the Ta-based case with SRAFs. Therefore, adoption of such high-k absorbers could potentially postpone the need for SRAFs.
A pupil optimization was carried out for the M2 layer of the imec N7 (foundry N5 equivalent) logic design. This is exposed as a single print EUV layer. We focused on the printability of the toughest parts of the design: a dense line space grating of 32 nm pitch and a tip-tip grating of 32 nm pitch, tip-to-tip target CD of 25 nm. We found that the pupil optimization can improve both the line space and the tip-to-tip gratings energy latitude and depth of focus. The tip-to-tip target CD can be pushed further, enabling further design scaling.
This paper summarizes findings for an N5 equivalent M2 (pitch 32) layer patterned by means of SE EUV. Different mask tonalities and resist tonalities have been explored and a full patterning (litho plus etch) process into a BEOL stack has been developed. Resolution enhancement techniques like SRAFs insertion and retargeting have been evaluated and compared to a baseline clip just after OPC. Steps forward have been done to develop a full patterning process using SE EUV, being stochastics and variability the main items to address.
In order to maintain the scaling trend in logic technology node progression, imec technology nodes started heavily utilizing design technology co-optimization (DTCO) on top of loosen pitch scaling trend to mitigate the burden from steep cost increase and yield challenge. Scaling boosters are adopted to enable DTCO process on top of patterning near its cliff to mitigate the cost increase. As the technology node further proceeds, DTCO also starts facing its cliff, and system technology co-optimization (STCO) is introduced to assist pitch and DTCO scaling to bridge 2-D IC technology to evolutionary technology options such as MRAM, 2.5-D heterogeneous integration, 3-D integration and 3-D IC. EUV is used to further assist pitch and DTCO scaling to maintain low cost with higher yield and faster turn-around-time (TAT). EUV single patterning, multiple patterning and high-NA EUV are considered on top of DTCO and STCO landscape to define imec technology nodes.
imec’s investigation on EUV single patterning insertion into industry 5nm-relevant logic metal layer is discussed. Achievement and challenge across imaging, OPC, mask data preparation and resulting wafer pattern fidelity are reported with a broad scope.
Best focus shift by mask 3D of isolated feature gets worse by the insertion of SRAF, which puts a negative impact on obtaining large overlap process window across features. imec’s effort across OPC including SMO and mask sizing is discussed with mask rule that affects mask writing. Resist stochastic induced defect is identified as a biggest challenge during the overall optimization, and options to overcome the challenge is investigated. For mask data preparation, dramatic increase in the data volume in EUV mask manufacturing is observed from iArF multiple patterning to EUV single patterning conversion, particularly by the insertion of SRAF. In addition, logic design consideration to make EUV single patterning more affordable compared to alternative patterning option is be discussed.
In the course of assessing OPC compact modeling capabilities and future requirements, we chose to investigate the interface between CD-SEM metrology methods and OPC modeling in some detail. Two linked observations motivated our study:
1) OPC modeling is, in principle, agnostic of metrology methods and best practice implementation.
2) Metrology teams across the industry use a wide variety of equipment, hardware settings, and image/data analysis methods to generate the large volumes of CD-SEM measurement data that are required for OPC in advanced technology nodes.
Initial analyses led to the conclusion that many independent best practice metrology choices based on systematic study as well as accumulated institutional knowledge and experience can be reasonably made. Furthermore, these choices can result in substantial variations in measurement of otherwise identical model calibration and verification patterns.
We will describe several experimental 2D test cases (i.e., metal, via/cut layers) that examine how systematic changes in metrology practice impact both the metrology data itself and the resulting full chip compact model behavior. Assessment of specific methodology choices will include:
• CD-SEM hardware configurations and settings: these may range from SEM beam conditions (voltage, current, etc.,) to magnification, to frame integration optimizations that balance signal-to-noise vs. resist damage.
• Image and measurement optimization: these may include choice of smoothing filters for noise suppression, threshold settings, etc.
• Pattern measurement methodologies: these may include sampling strategies, CD- and contour- based approaches, and various strategies to optimize the measurement of complex 2D shapes.
In addition, we will present conceptual frameworks and experimental methods that allow practitioners of OPC metrology to assess impacts of metrology best practice choices on model behavior.
Finally, we will also assess requirements posed by node scaling on OPC model accuracy, and evaluate potential consequences for CD-SEM metrology capabilities and practices.
imec’s DTCO and EUV achievement toward imec 7nm (iN7) technology node which is industry 5nm node
equivalent is reported with a focus on cost and scaling. Patterning-aware design methodology supports both
iArF multiple patterning and EUV under one compliant design rule. FinFET device with contacted poly pitch of
42nm and metal pitch of 32nm with 7.5-track, 6.5-track, and 6-track standard cell library are explored. Scaling
boosters are used to provide additional scaling and die cost benefit while lessening pitch shrink burden, and it
makes EUV insertion more affordable. EUV pattern fidelity is optimized through OPC, SMO, M3D, mask
sizing and SRAF. Processed wafers were characterized and edge-placement-error (EPE) variability is validated
for EUV insertion. Scale-ability and cost of ownership of EUV patterning in aligned with iN7 standard cell
design, integration and patterning specification are discussed.
Proc. SPIE. 10143, Extreme Ultraviolet (EUV) Lithography VIII
KEYWORDS: Oxides, Metrology, Data modeling, Calibration, Etching, Metals, Resistance, Photoresist materials, Finite element methods, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Optical proximity correction, Semiconducting wafers, Back end of line
Inpria has developed a directly patternable metal oxide hard-mask as a high-resolution photoresist for EUV lithography1. In this contribution, we describe a Tachyon 2D OPC full-chip model for an Inpria resist as applied to an N7 BEOL block mask application.
This paper summarizes findings on the iN7 platform (foundry N5 equivalent) for single exposure EUV (SE EUV) of M1 and M2 BEOL layers. Logic structures within these layers have been measured after litho and after etch, and variability was characterized both with conventional CD-SEM measurements as well as Hitachi contouring method. After analyzing the patterning of these layers, the impact of variability on potential interconnect reliability was studied by using MonteCarlo and process emulation simulations to determine if current litho/etch performance would meet success criteria for the given platform design rules.
The imec N7 (iN7) platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. Its design is based on a 42 nm first-level metal (M1) pitch, and a 32 nm pitch for the subsequent metal layers<sup>1</sup>. With these pitches, the iN7 node is an ‘aggressive’ full-scaled N7, corresponding to IDM N7, or foundry N5.<p> </p> Regarding the metal 2 layer, imec is evaluating two integration approaches: EUV single print and SAQP+EUV Block. Extensive work is reported on both approaches<sup>2,3</sup>. The work detailed in this paper will deal about the computational work done prior to tape-out for the EUV direct print option. <p> </p>We will discuss the EUV source mask optimization for an ASML NXE:3300 EUV scanner. Afterwards we will shortly touch upon OPC compact modeling and more extensively on OPC itself. Based on the current design rules and MRC, printability checks indicate that only limited process windows are obtained. We propose ways to improve the printability through MRC and design. Applying those changes can potentially lead to a sufficient process window.
Inpria continues to leverage novel metal oxide materials to produce high resolution photoresists for EUV lithography with high optical density and etch resistance. Our resists have previously demonstrated 13nm line/space patterns at 35 mJ/cm<sup>2</sup>, with extendibility to 10nm half-pitch.<sup>1</sup> We have continued to improve photospeed and in this work we provide an update on imaging performance. Since practical patterns for EUV layers will be more complicated than line/space patterns, we also expand on our previous work by demonstrating 2D resist performance using N7 (7nm node) contact and block mask patterns on full field scanners. A resist model has been created and using this model comparisons are made between a metal oxide resist and CAR platforms. Based on this physical model, the impact of shot noise is examined in relation to realistic 2D features. Preliminary data on the effect on OPC of using a non-chemically amplified resist are also presented.
In a 7 nm node (N7), the logic design requires a critical poly pitch of 42 to 45 nm and a metal 1 (M1) pitch of 28 to 32 nm. Such high-pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with a triple litho-etch (LE3) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent three-dimensional (3-D) profile and topology. We use this tool to study the patterning process variations of the N7 M1 layer including the overlay control, the critical dimension uniformity budget, and the lithographic process window (PW). The resulting 3-D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field, and identify hot spots for dielectric reliability. As an example application, the maximum electric field at M1 tip-to-tip, which is one of the most critical patterning locations, has been simulated and extracted. The approach helps to investigate the impact of process variations on dielectric reliability. We have also assessed the alternative M1 patterning flow with a single exposure block using extreme ultraviolet lithography (EUVL) and analyzed its advantages compared to the LE3 block approach.
This work addresses the difficulties in creating a manufacturable M2 layer based on an SADP process for N10/N7 and proposes a couple of solutions. For the N10 design, we opted for a line staggering approach in which each line-end ends on a contact. We highlight the challenges to obtain a reasonable process window, both in simulation as on based on exposures on wafer. The main challenges come from a very complex keep mask, consisting of complicated 2D structures which are very challenging for 193i litho. Therefore, we propose a solution in which we perform a traditional LELE process on top of a mandrel layer. Towards N7 we show that a line staggering approach starts to break down and design needs to allow better process window for lithography by having metal lines ending in an aligned fashion. has many challenges and we propose to switch to a line cut approach. A more lithography friendly approach is needed for design where the lines end at aligned points so that the process window can be enhanced.
In 7mn node (N7), the logic design requires the critical poly pitch (CPP) of 42-45nm and metal 1 (M1) pitch of 28- 32nm. Such high pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with triple litho-etch (LE<sup>3</sup>) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent 3D profile and topology. We use this tool to study the patterning process variations of N7 M1 layer including the overlay control, the critical dimension uniformity (CDU) budget and the lithographic process window (PW). The resulting 3D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field and identify hot spots for dielectric reliability. As an example application, we will report extractions of maximum electric field at M1 tipto- tip which is one of the most critical patterning locations and we will demonstrate the potential of this approach for investigating the impact of process variations on dielectric reliability. We will also present simulations of an alternative M1 patterning flow, with a single exposure block using extreme ultraviolet lithography (EUVL) and analyze its advantages compared to the LE<sub>3</sub> block approach.
While waiting for EUV lithography to become ready for adoption, we need to create designs compatible with both EUV single exposures as well as with 193i multiple splits strategy for technology nodes 7nm and below needed to keep the scaling trend intact. However, the standard approach of designing standard cells in two-dimensional directions is no more valid owing to insufficient resolution of 193-i scanner. Therefore, we propose a standard cell design methodology, which exploits purely one-dimensional interconnect.
The 20nm Metal1 layer, based on ARM standard cells, has a 2D design with minimum pitch of 64nm. This 2D design
requires a Litho-Etch-Litho-Etch (LELE) double patterning. The whole design is divided in 2 splits: Me1A and Me1B.
But solution of splitting conflicts needs stitching at some locations, what requires good Critical Dimension (CD) and
overlay control to provide reliable contact between 2 stitched line ends.
ASML Immersion NXT tools are aimed at 20 and 14nm logic production nodes. Focus control requirements become
tighter, as existing 20nm production logic layouts, based on ARM, have about 50-60nm focus latitude and tight CD
Uniformity (CDU) specifications, especially for line ends.
IMEC inspected 20nm production Metal1 ARM standard cells with a Negative Tone Development (NTD) process using
the Process Window Qualification-like technique experimentally and by Brion Tachyon LMC by simulations. Stronger
defects were found thru process variations. A calibrated Tachyon model proved a good overall predictability capability
for this process. Selected defects are likely to be transferred to hard mask during etch.
Further, CDU inspection was performed for these critical features. Hot spots showed worse CD uniformity than
specifications. Intra-field CDU contribution is significant in overall CDU budget, where reticle has major impact due to
high MEEF of hot spots. Tip-to-Tip and tip-to-line hot spots have high MEEF and its variation over the field. Best focus
variation range was determined by best focus offsets between hot spots and its variation within the field.
Computational lithography has become indispensable when developing lithography solutions for advanced technology nodes. One of the essential instruments for optimizing full-chip process windows (PW) is source mask optimization (SMO). To avoid model calibration for each new optimized source, separable resist models need to be created such that a reliable model can be obtained simply by replacing the source in the existing OPC model. In this paper we start from a fully calibrated resist model and optimize a new source for which we want to create a reliable OPC model. Relying on the separability of the model, the initial illumination source is replaced by the new one while not changing any resist model parameters. In order to reach the accuracy needed for OPC, the best focus and best dose still need to be accurately determined. We will investigate two models that have the same new SMO source and original resist model. For one model the best focus and dose are determined by the simulated Bossung plot of one anchor feature. The second model’s best focus and exposure are determined by a small set of FEM experimental data. The quality of these two models is then evaluated by comparing them to a reference model, which is fully calibrated using a complete dataset for the new source. We show that the calibrated FEM OPC model can be extrapolated by simply changing the source. A limited amount of experimental FEM data is required to accurately determine the best focus and exposure for the new source. Best focus and exposure based on the anchor pattern simulation has a higher degree of uncertainty compared to a small set of experimental data.
We report that in the absence of electric dipole contributions, upon azimuthal sample rotation, the
corresponding SHG response was found to be chiral, i.e. it shows the presence of asymmetries with a sense
of rotation (lack of mirror symmetry). It was found that this sense of rotation reverses with the handedness
configuration (G and mirror-G, see Fig. 1). While it is apparent that the property originates in local field
enhancements of electric and/or magnetic multipoles, its explanation invites further theoretical research.