The end of the performance entitlement historically achieved by classic scaling of CMOS devices is within sight, driven
ultimately by fundamental limits. Performance entitlements predicted by classic CMOS scaling have progressively failed
to be realized in recent process generations due to excessive leakage, increasing interconnect delays and scaling of gate
dielectrics. Prior to reaching fundamental limits, trends in technology, architecture and economics will pressure the
industry to adopt new paradigms. A likely response is to repartition system functions away from digital implementations
and into new architectures. Future architectures for visual communications will require extending the implementation
into the optical and analog processing domains. The fundamental properties of these domains will in turn give rise to
new architectural concepts. The limits of CMOS scaling and impact on architectures will be briefly reviewed. Alternative
approaches in the optical, electronic and analog domains will then be examined for advantages, architectural impact and drawbacks.
Image quality assessments for Intel's digital imaging chip set prototype are made using objective and subjective image quality assessment criteria. Objective criteria such as signal to noise ratio, linearity, color error, dynamic range, and resolution are used to provide quantitative metrics for engineering development. Subjective criteria such as mean observer scores derived from single stimulus and paired comparison adjectival ratings provide overall product image quality assessment that are used to determine product acceptability assessments for product marketing analysis. These metrics along with the subjective assessment, serve as development tools which allow the product development team to focus on the critical areas which improve the image quality of the product.