Ms. Whitney J. Townsend Profile

Whitney J. Townsend

at Univ of Texas at Austin

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Proceedings Article | 24 December 2003 Paper

A comparison of Dadda and Wallace multiplier delays

Whitney Townsend, Earl Swartzlander, Jacob Abraham

Proceedings Volume 5205, (2003) https://doi.org/10.1117/12.507012

KEYWORDS: Computer engineering, Logic, Signal processing, Computer architecture, Binary data

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The two well-known fast multipliers are those presented by Wallace and Dadda. Both consist of three stages. In the first stage, the partial product matrix is formed. In the second stage, this partial product matrix is reduced to a height of two. In the final stage, these two rows are combined using a carry propagating adder. In the Wallace method, the partial products are reduced as soon as possible. In contrast, Dadda's method does the minimum reduction necessary at each level to perform the reduction in the same number of levels as required by a Wallace multiplier. It is generally assumed that, for a given size, the Wallace multiplier and the Dadda multiplier exhibit similar delay. This is because each uses the same number of pseudo adder levels to perform the partial product reduction. Although the Wallace multiplier uses a slightly smaller carry propagating adder, usually this provides no significant speed advantage. A closer examination of the delays within these two multipliers reveals this assumption to be incorrect. This paper presents a detailed analysis for several sizes of Wallace and Dadda multipliers. These results indicate that despite the presence of the larger carry propagating adder, Dadda's design yields a slightly faster multiplier.

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