Improved overlay capability and sampling to control advanced lithography has accelerated the need for compact, multilayer/
mask/field/mark overlay metrology. The Blossom approach minimizes the size of the overlay marks associated
with each layer while maximizing the density of marks within the overlay metrology tool's field of view (FOV). Here
we describe our progress implementing this approach in 45nm manufacturing.
The lithographic challenges of printing at low-k1 for 65 nm logic technologies have been well-documented (1,2). Heavy utilization of model-based optical proximity correction (OPC) and reticle enhancement technologies (RET) are the course of record for 65 nm logic nodes and below. Within the SRAM cells, often more dimensionally constrained than random logic, characterization of the nominal gate linewidth and linewidth variation is critical to ensure cell performance and stability. In this paper, we present the use of the linewidth roughness analysis package of a commercially-available CD SEM to extract low-spatial frequency information in order to characterize effects of OPC, substrate topography, process variations, and RETs. The SEM-based characterization of across-device linewidth variation is analyzed statistically to extract the information necessary to set device processing conditions and to make layout corrections consistent with producing the least possible channel length variation along the active device.
A simple experimentally characterized lumped-parameter budget model is developed with the goal of quantifying the most significant components of critical dimension (CD) variation through an integrated process module. Tracked components include mask fabrication budgets, mask error factor, scanner field variation, optical proximity correction error, CD errors over chip topography, wafer-to-wafer and lot-to-lot variation. The components of variation are quantified for lithography and etch where appropriate and are fed into a simple interaction model to construct an overall patterning module CD budget. Normalized experimental results for this budget analysis are presented for 65 nm technology node contact patterning processes.
With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications.
This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our team's success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.
This paper investigates the implementation of sub-resolution assist features (SRAFs) in high performance logic designs for the poly-gate conductor level. We will discuss the concepts used for SRAF rule generation, SRAF data preparation and what we term "binary" optical proximity correction (OPC) to prevent catastrophic line-width problems. Lithographic process window (PW) data obtained with SRAFs will be compared to PW data obtained without SRAF. SRAM cells are shown printed with annular illumination and SRAFs, for both the 130 nm and 100 nm logic nodes as defined by the International Technology Roadmap for Semiconductors (ITRS). This study includes a comparison of the experimental results of SRAMs printed from designs corrected with rule-based OPC to those printed from designs corrected with model-based OPC.
Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBM's early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.
On-product or 'output' dose and contrast variations (the temporal and spatial changes to image intensity and modulation captured in the developed wafer pattern) are the dominant contributors to across-field and across-wafer critical dimension (CD) variation. While the 'input' dose and focus degrees of freedom of step-and-scan tools offer the potential for improved CD control, its realization at low k1 depends on our ability to adjust tool settings such that the output contrast is maximized and the output dose is clamped to a desired operating point. Our paper describes our application of output dose and contrast, derived from the measurement of on-product targets, to the CD characterization of step-and- scan lithography at 150 nm ground rules and below. We demonstrate the means for simultaneous input dose and focus correction and quantify the consequent benefit to CD control.
This paper is the third of a series that defines a new approach to in-line lithography control. The first paper described the use of optically measurable line-shortening targets to enhance signal-to-noise and reduce measurement time. The second described the dual-tone optical critical dimension (OCD) measurement and analysis necessary to distinguish dose and defocus. Here we describe the marriage of dual-tone OCD to SEM-CD metrology that comprises what we call 'process window metrology' (PWM), the means to locate each measured site in dose and focus space relative to the allowed process window. PWM provides in-line process tracking and control essential to the successful implementation of low-k lithography.