There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors
(CMPs) will be the power efficiency and the available communication speed between cores. Photonic
Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection
bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer
distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings,
photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC
proposals exist, their use is often limited to the communication of large data messages due to a relatively long
set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the
topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings.
To evaluate this system's performance, the proposed architecture has been implemented in a detailed
full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In
addition, a model was developed to estimate the power consumption of the full interconnection network which
was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture
significantly lowers the average memory access latency (35% reduction) while only generating a modest increase
in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When
comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can
be tolerated which makes our approach directly applicable to current shared-memory CMPs.
Communication between processors and memories has always been a limiting factor in making efficient computing
architectures with large processor counts. Reconfigurable interconnection networks can help in this respect, since they
can adapt the interconnect to the changing communication requirements imposed by the running application, and optical
technology and photonic integration allow for an easy implementation of such adaptable systems. In this paper, we
present a proposed reconfigurable interconnection network in the context of distributed shared-memory multiprocessors.
We show through full-system simulation of benchmark executions that the proposed system architecture can provide a
significant speedup for shared-memory machines, even when physical limitations due to low-cost optical components are
introduced. We propose then a reconfigurable optical interconnect implementation, making use of tunable sources and a
selective broadcasting component, and we report on the first fabricated optical components of the design: refractive
microlenses, fiber connectors, microprism holders and alignment plates.
Nowadays, multiprocessor systems are reaching their limits due to the large interconnection bottleneck between chips, but recent advances in the development of optical interconnect technologies can allow the use of low cost, scalable and reconfigurable networks to resolve the problem. In this paper, we make an initial evaluation of the performance gain on general network reconfigurability. In a next stage, we propose an optical system concept and describe a passive optical broadcasting component to be used as the key element in a broadcast-and-select reconfigurable network. We also discuss the available opto-electronic components and the restrictions they impose on network performance. Through detailed simulations of benchmark executions, we show that the proposed system architecture can provide a significant speedup for shared-memory machines, even when taking into account the limitations imposed by the opto-electronics and the presented optical broadcast component.
Electrical interconnection networks connecting the different processors and memory modules in modern large-scale multiprocessor machines are running into several physical limitations. In shared-memory machines, where the network is part of the memory hierarchy, high network latencies cause a significant performance bottleneck.
Parallel optical interconnection technologies can alleviate this bottleneck by providing fast and high-bandwidth links. Moreover, new devices like tunable lasers and detectors or MEMS mirror arrays allow us to reconfigure the network at runtime in a data transparent way. This allows for extra connections between distant node pairs that communicate intensely, achieving a high virtual network connectivity by providing only a limited number of physical links at each moment in time.
In this paper, we propose a reconfigurable network architecture that can be built using available low cost components and identify the limitations these components impose on network performance. We show, through detailed simulation of benchmark executions, that the proposed network can provide a significant speedup for shared-memory machines, even with the described limitations.