A tiny footprint electrically probable single layer defocus monitor/test structure has been designed and tested to show
sub-10nm resolution in electrical or electronic defocus monitoring. Electronic testing is a low-cost must have for on-chip
production process monitoring which will become necessary for effective Design for Manufacturing. This programmable
defocus monitor can be designed to pinch open at various levels of defocus by modifying four different layout
parameters, CD, probe size, offset, and the number of rings. An array of these structures can be read as a series of opens
and shorts, or 1s and 0s, to electronically extract defocus. One important feature of this defocus test structure is that it has
an asymmetric response through focus, which translates to a high sensitivity to defocus at low defocus values or close to
nominal conditions. Simulation and experimental results have shown good sensitivity for both on axis, tophat, and offaxis,
quasar, illumination. This paper will present both simulation and experimental results that demonstrate the
programmability and sensitivity of this test structure to defocus.
This paper applies process and circuit simulation to examine plausible explanations for measured differences in ring
oscillator frequencies and to develop layout and electronic circuit concepts that have increased sensitivity to
lithographic parameters. Existing 90nm ring oscillator test chip measurements are leveraged, and the performance
of ring oscillator circuit is simulated across the process parameter variation space using HSPICE and the Parametric
Yield Simulator in the Collaborative Platform for DfM. These simulation results are then correlated with measured
ring oscillator frequencies to directly extract the variation in the underlying parameter. Hypersensitive gate layouts
are created by combining the physical principles in which the effects of illumination, focus, and pattern geometry
interact. Using these principles and parametric yield simulations, structures that magnify the focus effects have been
found. For example, by using 90° phase shift probe, parameter-specific layout monitors are shown to be five times
more sensitive to focus than that of an isolated line. On the design side, NMOS or PMOS-specific electrical
circuits are designed, implemented, and simulated in HSPICE.
A database and data analysis strategy is proposed for multi-designer test chips that involve a wide array of different test
structures aimed at process characterization. The database described in this paper has been custom built for the multi-student
FLCC testchip that has six contributing students and over 15,000 individually probably transistors/test
structures. It has an interface with the Parametric Yield Simulator (PYS) that drives simulation parameters and
automatically populates the database with simulation results of each test structure at the specified process conditions. A
well-designed database forces structure into measurement and design related data, but includes enough flexibility as to
adapt to different types of test structures and experiments. The database is split into four separate sections that store
description of test structures, simulated results, experiment results, and process conditions. All data is centrally located
and web accessible for easy access from any computer with Internet access. Simulation results can be uploaded from the
server running the PYS, experimental results can be uploaded directly from the lab and data can be compared and
queried by all users of the database. Data analysis strategies can be compared and reused as queries and data analysis
results can be shared among users through the website. Queries can be saved, loaded, rated, and reused, so even novice
SQL users can utilize advanced queries. Advanced queries form the basis of a strategy that first identifies good process
monitors based on simulation results and then uses them to extract process conditions from electrical measurements via
an iterative process. This paper describes strategies that can be used to help facilitate collaboration and hence leverage
the benefits of combining multiple sets of test structures from different designers on one chip.
A multi-student testchip aimed at characterizing lithography related variations with over 15,000 individually probable
test structures and transistors has been designed and a complementary 65nm process flow and data aggregation strategy
have also been implemented. Test structures have been strategically designed to have high sensitivities to non-idealities
such as defocus, LWR, misalignment and other systematic sources of variation. To enable automated measurement of
massive amounts of test structures, Enhanced Transistor Electrical CD (Critical Dimension) metrology has been used as
it offers high pattern density and almost no geometrical restrictions. Electrical testing at cryogenic temperatures will be
employed to study the impact of Line Width Roughness (LWR) versus Random Dopant Fluctuations (RDF), which will
not play a significant role at cryogenic temperatures, 4K. To facilitate data analysis and comparison of results between
students, a relational database has been designed and implemented. The database will be web accessible for each student
to use and update. It will serve as a collaborative platform for reinforcing conclusions, filtering out confounding data,
and involving outside parties that are interested in process variations at the 65nm node. Experimental data was not
available at the time this paper was written, so this paper will concentrate on the design and simulation results of test
Exploratory prototype DfM tools, methodologies and emerging physical process models are described. The examples
include new platforms for collaboration on process/device/circuits, visualization and quantification of manufacturing
effects at the mask layout level, and advances toward fast-CAD models for lithography, CMP, etch and photomasks. The
examples have evolved from research supported over the last several years by DARPA, SRC, Industry and the Sate of
California U.C. Discovery Program. DfM tools must enable complexity management with very fast first-cut accurate
models across process, device and circuit performance with new modes of collaboration. Collaborations can be promoted
by supporting simultaneous views in naturally intuitive parameters for each contributor. An important theme is to shift
the view point of the statistical variation in timing and power upstream from gate level CD distributions to a more
deterministic set of sources of variations in characterized processes. Many of these nonidealities of manufacturing can be
expressed at the mask plane in terms of lateral impact functions to capture effects not included in design rules. Pattern
Matching and Perturbation Formulations are shown to be well suited for quantifying these sources of variation.
The variability in the printing of small contacts with electron-beam lithography in a fast high resolution resist was characterized using automated SEM image analysis of an identical array of contact holes. The goal of this study was to evaluate the sources and severity of pattern noise in an e-beam system. A matrix of 391 contacts, 17x23 (dictated by the dimensions of the SEM display 768x1024), was printed at 100KeV on the LBNL nano-writer in KRS-XE2 photoresist. The doses ranged from 28uC/cm∧2 to 851uC/cm∧2 with 8nm, 16nm, 24nm, 32nm, and 40nm contact holes. Printed contacts were counted by image processing of SEM images using NIH's ImageJ program. The amount of pattern noise was found to be 14X larger than the noise that would be predicted by the traditional Poisson shot noise of 5500 electrons per contact. Surprisingly, the pattern noise was independent of PEB time and resist thickness. The main source of noise was found to be associated with the surface of the resist, most likely outgassing of acid in the e-beam vacuum chamber. The contact hole experiment provides a practical method for quantifying random effects in evaluating resists, processes, and treatments.
A pattern matching technique for quickly scanning layouts to find 'worst case' printing problems has been extended to and tested for accuracy on a progressive sequence of advances in optical lithography, including off-axis illumination, attenuated masks, optical-proximity correction and double exposure treatments. These extensions required including phase-variations from off-axis sources with the usual method for production of Maximum Lateral Test Patterns, and utilizing a composite match factor computer from McIntyre et al. to give a vulnerability score. Direct aerial image simulation of the projection printing of the local pattern shows that the basic trends are correctly extracted at high-speed with pattern matching. Pattern matching is found to be a useful tool under these technologies for prescreening layouts to find the most sensitive areas to residual effects, and also for quick comparison of worst case issues among different lithography treatments.
A Process/Device/Design framework called the Parametric Yield Simulator is proposed for predicting circuit variability based on circuit design and a set of characterized sources of variation. In this simulator, the aerial image of a layout is simulated across a predefined process window and resulting non-idealities in geometrical features are communicated through to circuit simulators, where circuit robustness and yield can be evaluate in terms of leakage and delay variability. The purpose of this simulator is to identify problem areas in a layout and quantify them in terms of delay and leakage in a manner in which designers and process engineers can collaborate together on an optimal solution to the problem. The Parametric Yield Simulator will serve as a launch pad for collaborative efforts between groups in different disciplines that are looking at variability and yield. Universities such as Berkeley offer a great advantage in exploring innovative approaches as different centers of key expertise exist under one roof. For example a complementary set of characterization and validation experiments has also been designed and in a collaborative study is being executed at Cypress semiconductor on a 65nm NMOS process flow. This unique opportunity of having access to a cutting edge process flow with relatively high transparency has led to a new set of experiments with contributions from six different students in circuit design, process engineering, and device physics. Collaborative efforts with the device group have also led to a new electrical linewidth metrology methodology using enhanced transistors that could prove useful for process characterization.
Non-rectangular transistors in today's advanced processes pose a potential problem between manufacturing and design as today's compact transistor models have only one length and one width parameter to describe the gate dimensions. The transistor model is the critical link between manufacturing and design and needs to account for across gate CD variation as corner rounding along with other 2D proximity effects become more pronounced. This is a complex problem as threshold voltage and leakage current have a very complex non-linear relationship with gate length. There have been efforts trying to model non-rectangular gates as transistors in parallel, but this approach suffers from the lack of accurate models for "slice transistors", which could potentially necessitate new circuit simulators with new sets of complex equations. This paper will propose a new approach that approximates a non-rectangular transistor with an equivalent rectangular transistor and hence does not require a new transistor model or significant changes to circuit simulators. Effective length extraction consists of breaking a non-rectangular transistor into rectangular slices and then taking a weighted average based on simulated slice currents in HSPICE. As long as a different effective length is used for delay and static power analysis, simulation results show that the equivalent rectangular transistor behaves the same as a non-rectangular transistor.
The quencher mechanisms in Chemically-Amplified (CA) resists have been investigated. To explain the acid distribution with a variety of acid strengths in the presence of quencher, a new full Acid-Equilibrium-Quencher model (AEQ model) is proposed and examined in solid-model-CA-resist systems. To observe the reactions in the CA resists, real-time Fourier-Transform-Infrared Spectroscopy (FTIR) is employed during post-exposure bake (PEB). The FTIR peaks of the protection groups are detected to measure the reaction kinetics during PEB. The solid-model-CA resists used in this work consist of both a KrF-acetal-type resist with a diazomethane Photo-Acid Generator (PAG) (weaker-photoacid system) and an ArF-ester-type resist with a sulfonium-salt PAG (stronger-photoacid system). The obtained FTIR results are analyzed using conventional Full-Dissociation-Quencher model (FDQ model) and the new AEQ model. The kinetic analysis of the model resists was performed for different quencher loadings. For the weaker-photoacid system, the AEQ model much more accurately predicts the deprotection-reaction kinetics than the FDQ model with the change of quencher content. This suggests the necessity of introduction of the acid-dissociation concept in the case of the weaker photoacid. For the stronger-photoacid system, both the AEQ and conventional FDQ models adequately predict the kinetic results. This shows that the conventional FDQ model is accurate enough to simulate the super-strong photoacid system. Finally, the new AEQ model is introduced in the UC Berkeley STORM resist simulator. Some simulation examples are shown in the paper.
This paper describes a systematic and rigorously controlled set of experiments showing the effectiveness of the Electric Field Enhanced Post Exposure Bake (EFE-PEB) with 248nm KrF(ASML) exposures on Apex-E photoresist (IBM) where feature sizes ranged from 0.3 um to 0.5 um. Experimental results showed a significant improvement in process latitude and resist sensitivity for features with a k1 technology factor of 0.68 and below. The experiments were executed using a 248nm KrF stepper (ASML), NA 0.5, and Apex-E photoresist (IBM), which has a relatively high acid diffusivity. An improved experimental setup rigorously controls PEB time, PEB temperature, development time, focus drift, and other environmental variables. Cross sectional SEMs of five line arrays with L=S ranging from 337nm to 500 um show deeper trenches when the electric-field treatment was used. Exposures that were intentionally out of focus cleared 600nm deep in 1um thick photoresist in the control group, but did clear the full 1um with the application of the Electric Field during the PEB. A dose matrix experiment showed an 8% decrease in the dose to clear and two-fold increase in focus latitude. This comprehensive study demonstrated an increase in anisotropic acid diffusivity with the application of the electric field and confirmed that the EFE-PEB offers a relatively inexpensive and simple method for improving photoresist performance.