Despite the large difficulties involved in extending 193i multiple patterning and the slow ramp of EUV lithography to full manufacturing readiness, the pace of development for new technology node variations has been accelerating. Multiple new variations of new and existing technology nodes have been introduced for a range of device applications; each variation with at least a few new process integration methods, layout constructs and/or design rules. This had led to a strong increase in the demand for predictive technology tools which can be used to quickly guide important patterning and design co-optimization decisions.
In this paper, we introduce a novel hybrid predictive patterning method combining two patterning technologies which have each individually been widely used for process tuning, mask correction and process-design cooptimization. These technologies are rigorous lithography simulation and inverse lithography technology (ILT). Rigorous lithography simulation has been extensively used for process development/tuning, lithography tool user setup, photoresist hot-spot detection, photoresist-etch interaction analysis, lithography-TCAD interactions/sensitivities, source optimization and basic lithography design rule exploration. ILT has been extensively used in a range of lithographic areas including logic hot-spot fixing, memory layout correction, dense memory cell optimization, assist feature (AF) optimization, source optimization, complex patterning design rules and design-technology co-optimization (DTCO). The combined optimization capability of these two technologies will therefore have a wide range of useful applications. We investigate the benefits of the new functionality for a few of these advanced applications including correction for photoresist top loss and resist scumming hotspots.
As minimum feature size shrinks to a metal pitch of 21 nm, the current extreme ultra violet (EUV) lithographic tool with a numeric aperture (NA) of 0.33 will face resolution limit for some critical layers. High NA (0.55) EUV with anamorphic optics or EUV double patterning (DP) at 0.33 NA are being considered for the next generation of lithographic technology. Both the high NA EUV system and EUV DP will enhance resolution relative to current EUV single patterning (SP). Nevertheless, in order to be able to compare EUV DP and High NA EUV processes, important lithographic factors including image contrast, mask three dimension (M3D) effects, process variation band, stochastic effects and local critical dimension uniformity need to be investigated to understand their contributions to process variations. This study was carried out using rigorous lithographic model simulations in Sentaurus Lithography, where strong M3D effects in EUVL are computed physically. We have simulated patterns with both isomorphic and anamorphic optical proximity corrections (OPC) using the rigorous model. The study focuses on 3nm node Via layer designs. These vias need to connect to metal features which have pitches of 21 nm. Simulation results using 0.33 NA SP, 0.33 NA DP, and 0.55 NA anamorphic SP are presented. The benefit of using an alternative mask absorber and a thinner resist as well as the impact of stochastic effects have also been explored. Although a 0.55 NA EUV is expected to produce a superior image to 0.33 NA EUV and to have less impact from overlay errors and stochastic effects, an analysis of process margins of 0.33 NA EUV SD and DP versus 0.55 NA anamorphic systems helps to better understand the benefits, challenges and optimal insertion point for introducing High-NA EUV.
New inverse methods such as model-based SRAF placement, model-based SRAF optimization, and full main + assist
feature ILT are well known to have considerable benefits in finding flexible mask pattern solutions to improve process
window and CD control. These methods have traditionally relied on compact models that are tuned to match resist
measurements at a single z-height or slice. At this slice in the resist, some critical failure modes such as top loss and
scumming are not detected. In this paper, we describe and present results for a methodology to extend ILT’s process
window improvement capabilities, and to co-optimize mask patterns with awareness of the resist profile. These
improvements are proven to reduce the risk of patterning failures at the bottom and top of critical resist features, which a
typical mask correction process would not alleviate. Ideally, mask optimization would use a full rigorous TCAD resist
model to guide the correction at multiple heights in the resist. However, TCAD models are significantly slower than
compact models in simulations and ILT already has high computational requirements. Therefore, we have generated
compact models which are fitted to the TCAD model resist profile data. We show the significant process window
improvements obtained with this new resist 3D aware ILT methodology.
While critical lithographic feature size diminishes, resist profile can vary significantly as image varies. As a consequence, the final etch results are becoming more dependent on 3D resist profile rather than only a simple 2D resist image as an etch mask. Therefore, it has become necessary to build resist profile information into OPC models, which traditionally only contain 2D information in the x-y plane. At the same time, rigorous lithographic simulators are capable of modeling 3D resist profiles on a small chip area. In this work, one approach is investigated to account for 3D resist profile characteristics in full-chip OPC models with the assistance of rigorous simulation. With measurement data collected from experimental wafers, a rigorous resist model is first calibrated and verified. Then individual compact models are built to match the rigorous resist model profile at specified resist heights. The calibrated compact model for bottom resist line width corresponds to a conventional OPC model while resist profile is described by multiple models specified for certain resist heights, with each model being in the form of conventional compact models. In practice, the bottom model along with one or two models at critical heights are usually sufficient to detect sites where etch results become sensitive to resist profile. It has been found that the rigorous resist profile model can be well matched by the suggested compact models. For a quick application demonstration, hot spots of the etch results in the test case have been shown to be successfully captured by the calibrated compact models.
Proc. SPIE. 7748, Photomask and Next-Generation Lithography Mask Technology XVII
KEYWORDS: Electron beam lithography, Data modeling, Scattering, Calibration, Computer simulations, Scanning electron microscopy, Monte Carlo methods, Photoresist processing, Process modeling, Chemically amplified resists
With the constantly improving maturity of e-beam direct write exposure tools and processes for applications in high volume
manufacturing, new challenges with regard to speed, throughput, correction and verification have to be faced. One objective
of the MAGIC high-throughput maskless lithography project  is the application of the physics-based simulation in a
virtual e-beam direct write environment to investigate proximity effects and develop comprehensive correction
methodologies . To support this, a rigorous e-beam lithography simulator for the feature scale has been developed . The
patterning behavior is determined by modeling electron scattering, exposure, and resist processing inside the film stack, in
analogy with corresponding simulation capabilities for the optical and EUV case. Some model parameters, in particular for
the resist modeling cannot be derived from first principles or direct measurements but need to be determined through a
To gain experience with the calibration of chemically amplified resists (CAR) for e-beam lithography, test pattern exposures
have been performed for a negative tone CAR using a variable-shaped beam writer operating at 50kV. A recently
implemented model calibration methodology has been applied to determine the optimum set of resist model parameters.
While the calibration is based on 1D (lines & spaces) patterns only, the model results are compared to 2D test structures for
KEYWORDS: Point spread functions, Cadmium, Data modeling, Error analysis, 3D modeling, Critical dimension metrology, Geometrical optics, Virtual reality, Electron beam direct write lithography, Model-based design
We demonstrate a flow for e-beam proximity correction (EBPC) to e-beam direct write (EBDW) wafer manufacturing
processes, demonstrating a solution that covers all steps from the generation of a test pattern for (experimental or virtual)
measurement data creation, over e-beam model fitting, proximity effect correction (PEC), and verification of the results.
We base our approach on a predictive, physical e-beam simulation tool, with the possibility to complement this with
experimental data, and the goal of preparing the EBPC methods for the advent of high-volume EBDW tools.
As an example, we apply and compare dose correction and geometric correction for low and high electron energies on
1D and 2D test patterns. In particular, we show some results of model-based geometric correction as it is typical for the
optical case, but enhanced for the particularities of e-beam technology.
The results are used to discuss PEC strategies, with respect to short and long range effects.
For advanced technology nodes, a large amount of effort must be spent to optimize area critical full-custom layouts with respect to their manufacturability. Due to the strong irregularity and two-dimensionality of these layouts, it appears impossible to fully capture the corresponding complex requirements with design rules in order to be able to perform a rule-based physical verification in form of a "design rule check" (DRC). Alternative approaches have to be found and one of them is presented in this paper. The complexity of the DRC can be significantly reduced for rules focused on process aspects. Those rules can be replaced by a "simulation rule check" (SRC), where at first process simulations (like e.g. lithography) are done and then a set of straightforward rules is applied to geometrical entities representing the simulation output instead of the layout geometry. Thus, this new set of rules works more directly on the core of the matter. The "litho-friendly design environment" (LFD) provided by Mentor Graphics offers the tools for this approach. The SRC includes intra-layer checks like area, width, and space checks as well as interlayer checks, such as overlap. To the physical designer, SRC violations are presented in a DRC like fashion, including error scoring and classification. This paper will demonstrate the application of LFD and highlight the usability of this infrastructure for layout optimization using an SRC for physical verification.
For the technology development of microlithography various optical simulation tools are established as a planning and development tool. Depending on the application, various numerical approximation schemes are used to tradeoff accuracy versus speed. Determining the correct numerical setting is often a tricky task as it is a compromise between these two contrary properties. In our study, we compare the numerical accuracy of two optical simulators, Solid-E as a representative for simulators for technology development and Mentor Calibre as design-for-manufacturing and optical proximity correction (OPC) tool. Calibre uses a coherent kernel approximation for performing fast simulations. As a measure for the simulation accuracy, we use the root-mean-square error criterion of a linearity curve compared to an analytical reference simulation.
As in optical lithography, E-beam lithography is facing a multitude of issues, both in mask making and in direct write applications. These issues range from pattern printability and design verifications to tool and process optimizations. Simulation can be used to address these issues, however its applicability was limited due to limitations in the usable simulation area. Advances in the mathematical models lead to a significant speedup of the simulation, enabling the simulation of larger areas. This paper will demonstrate the applicability of the new simulator on a few key examples, such as aggressive mask challenges, model to experiment correlations as well as its application to direct write.
In this paper we examine new models and the indispensability of model parameters of chemically amplified resists (CAR) for their usage in predictive process simulation. Based on a careful exploration of different modeling options we calibrate the model parameters with different experimental data. Furthermore, we investigate different modeling approaches: (1) Mode of coupling between diffusion and kinetic reactions, sequence of quencher base events (Hinsberg model); (2) Mode of diffusion: Fickian and linear diffusion model; (3) Development rate model: Performance of the Enhanced Notch model. The resulting models are evaluated with respect to their performance by comparing with experimental line-width for semidense (1-2, 1-1.6, 1-1.4, 1-1.2) and dense features, the bias between different features and full resist profiles. The investigations are applied to the Shipley resist UVTM 113. Finally, a parameter extraction procedure for chemically amplified resists is proposed.
Proc. SPIE. 4345, Advances in Resist Technology and Processing XVIII
KEYWORDS: Lithography, Data modeling, Diffusion, Inspection, Photoresist materials, Promethium, Photoresist processing, Process modeling, Standards development, Picture Archiving and Communication System
The use of experimental development rate information is used to demonstrate various deficiencies in the dissolution rate equations commonly employed in commercial lithography simulation programs. An improved version of the Notch dissolution rate equation, incorporating one new parameter, is proposed, which addresses the observed deficiencies. Simulation work comparing the new equation to the standard Notch model reveals significant differences in process window and exposure margin, yet negligible changes in feature profile and iso-dense bias at best focus and exposure.
Lithography simulators have become a standard tool in industrial and governmental research and development departments. IN contrast to the modeling approaches for the optical system and for the lithographic performance of i- line resists, there is still no consensus on the modeling of chemically amplified resist (CAR). Existing models differ in the description of the kinetics and the diffusion phenomena during post exposure bake and in the specification of the development rate. A modeling approach was established, that combines the light induced generation of photoacid, in- and out-diffusion of acid or base components, a generalized deprotection kinetics, Fickian and non-Fickian diffusion of resist components and an arbitrary development rate model. Existing models such as the effective acid model and a standard deprotection model for CAR can be considered as special cases of the implemented model. To evaluate the importance of certain options of the model and of the model parameters we have evaluated the performance of the model by comparing simulated CD data and resists profiles with experimental data.