This paper presents a unified description of phase noise and timing jitter of oscillators and PLLs based on diffusion theory. Analytical expressions for period jitter, cycle-to-cycle jitter, and absolute jitter are derived and related to the power spectral density of the excess phase and the relative single-sideband phase noise of the oscillator. In addition to white noise sources resulting in phase diffusion, the effects of flicker noise and noise in the control voltages including supply and substrate noise are considered. More specifically, the absolute rms jitter of a PLL is related to the white and the flicker noise of a free-running oscillator. For an experimental 60 GHz oscillator fabricated in a 0.25 μm SiGe:C BiCMOS technology a phase noise of -90 dBc/Hz is measured at
1 MHz offset. From this measurement, an absolute rms jitter contribution of 70 fs is predicted for a 5 MHz bandwidth PLL.
This paper describes the design of noise-critical circuits for radio-frequency and high-speed digital applications in a SiGe:C BiCMOS technology. Starting with a figure of merit for the high-frequency noise behavior of bipolar transistors, challenges in the transistor design are formulated. It is shown that the addition of carbon to the base of a SiGe-HBT results in an excellent high-frequency noise behavior of the transistors. A first design of a differential three-stage low-noise amplifier for 60 GHz applications is presented having a gain of 18 dB at 50 GHz. Furthermore, a 60 GHz voltage-controlled oscillator is presented with a phase noise of -90 dBc/Hz at 1 MHz offset from the oscillation frequency. Using a first-order PLL model, we predict an rms jitter contribution to a 5 MHz-bandwidth PLL as low as 0.4 percent of the oscillation period. Possible applications include wireless and wired broadband communication as well as automotive radar.