With the introduction of sub100nm nodes lithography faces drastically decreasing process windows and ever more demanding CD specifications at the same time. Inline process control usually allows only a few measurement sites per wafer due to throughput limitations at the CD metrology tool. The drawback is that these data do not show the real process capability with respect to CD control. Such a comparatively small number of measurement sites provides only limited information about systematic signatures of the investigated processes. However, during the setup of design rules it is assumed that CD deviations are purely statistical. Moreover, the CD budget is statistically divided into a certain ratio between the involved process steps (i.e. mask process, lithography and etch). As systematic effects cannot be taken into account in this procedure there arises the necessity to investigate the major signatures of all involved process steps and to minimize them as much as possible. This paper presents the recent CD uniformity analysis results of different critical low k1 lithography layers and the following etch process steps. In particular a line/space level and a contact hole level of a 90nm state of the art DRAM process in the 300mm line are investigated as part of the design rule verification. Inline sampling results and results from extensive intra field, intra wafer and wafer to wafer measurements are compared. Inline sampling gives a slightly different overall CD performance than the extensive measurements. This deviation can be explained by the strong systematic effects which dominate intra field and intra wafer CD uniformity after all process steps. Their major source is found to be at certain etch processes. As a consequence of these results the inline sampling plan must be adjusted and systematic effects with a focus on the etch processes have to be reduced as much as possible.
In DRAM technology, rapidly decreasing critical dimensions cause a strong need in lithography for optimization of illumination conditions. In critical line levels, this will lead to an increasing demand for application of different, specially optimized illuminations to differently structured layout portions. Such a strategy can be achieved by double exposure techniques. A major technical challenge in this approach is the case in which electrically connected layout regions are assigned to different litho illuminations. Here, the layout separation onto different masks must preserve a sufficient process window in the electrically connected layout cut regions. A key success factor is a double exposure aware OPC strategy, able to describe and correct layouts defined by the interaction of two exposures with different illumination settings. In our contribution, we present the results of a double exposure experiment for a critical metal level. A likewise mask-manufacturing-friendly and litho-friendly method of layout separation on 'double tri-tone masks' was developed. Mask and wafer results show the principal feasibility of the chosen concept and prove the necessary OPC functionality.
Generally, the potential impact of systematical overlay errors on 300mm wafers is much larger than on 200mm wafers. Process problems which are merely identified as minor edge yield detractors on 200mm wafers, can evolve as major roadblocks for 300mm lithography. Therefore, it is commonly believed that achieving product overlay specifications on 300mm wafers is much more difficult than on 200mm wafers. Based on recent results on high volume 300mm DRAM manufacturing, it is shown that in reality this assumption does not hold. By optimizing the process, overlay results can be achieved which are comparable to the 200mm reference process. However, the influence of non-lithographic processes on the overlay performance becomes much more critical. Based on examples for specific overlay signatures, the influence of several processes on the overlay characteristics of 300mm wafers is demonstrated. Thus, process setup and process changes need to be analyzed monitored much more carefully. Any process variations affecting wafer related overlay have to be observed carefully. Fast reaction times are critical to avoid major yield loss. As the semiconductor industry converts to 300mm technology, lithographers have to focus more than ever on process integration aspects.
SEMICONDUCTOR300 was the first pilot production facility for 300mm wafers in the world. This company, a joint venture between Infineon Technologies Motorola, started in early 1998 to develop processes and manufacture products using 300mm wafer tool set. The lithography tools include I-line steppers, as I-line scanner, a DUV stepper, and DUV scanners. All of these exposure tools are running in-line with a photoresist coat and develop track. The lithography tools are used to build 64Mb DRAM devices and aggressive test vehicles with design rules of 0.25 micrometers and below, in sufficient quantity to be able to assess the tool readiness. This paper present the history of technical improvements and roadblocks that have occurred on the 300mm lithography tool set since the start-up, and describe a methodology used to assess the tool performance.
SEMICONDUCTOR300 was the first pilot production facility for 300mm wafers in the world. This company, a joint venture between Infineon Technologies and Motorola, is working to develop a manufacturable 300mm wafer tool set. The lithography tools include I-line steppers, a DUV stepper, and two DUV scanners. These tools are used to build 64M DRAM devices and aggressive test vehicles. Data will be presented on the mix-and-matching performance between DUV scanners and I-line steppers. Process-related data on CD within-field and across wafer sampling for selected tool types were investigated. The process capability of the current tool set for 0.25 micrometers and 0.18 micrometers devices were compared. Resolution performance of the scanner with its 0.68 numerical aperture was studied. Dense and isolated printed pattern performance was measured with in-line metrology. 300mm wafers are sensitive to backside defectivity, and therefore the wafer chuck design plays an important role in achieving the desired pattern transfer performance. The performance of the different chuck types and their sensitivity to incoming backside wafer contamination levels was studied. Rework data was used to assist in characterizing the exposure dose matching and chuck type performance.