In recent years ArF immersion lithography in memory devices, topcoat process has become baseline process in mass
production in spite of its additional process steps and high cost-of-ownership. In order to overcome low process
efficiency of topcoat process, high throughput scanner with higher scan speed and advanced rinse modules for
decreasing defectivity are under development. Topcoat-less resist is also upgraded gradually which contains
hydrophobic additives enables the extreme patterning without topcoat and high speed scanning. But current topcoat-less
process has not matured yet for the dark-field mask compared to bright-field because of the blob defect in unexposed area. To minimizing blob defect level both material and process sequence should be optimized effectively. The authors have focused on blob defect and litho performance of topcoat-less resist process for dark field application in 2Xnm node devices.
As a design rule shrink down aggressively, various RETs (Resolution Enhancement Technology) have been
developed to extend the resolution limits of lithography. Until now, next generation lithography has been focused on
EUV technology. But no one can assure when EUV will be implemented. So, we must develop new technology with
current immersion tool to catch up with aggressive design rule. One of those is DPT (Double Patterning Technology),
however there are also many challenges to overcome such as patterning, overlay, hard mask etch and so on. The most
critical issue would be overlay, because it affects CD (Critical dimension) uniformity directly. Therefore, overlay
control is very important between 1<sup>st</sup> DP layer and 2<sup>nd</sup> DP layer. We utilized ArF immersion scanners for this experiment.
In this paper, DP process flow, hard mask film dependency, align method dependency, efforts of new align key design
and direct align analysis in DP overlay will be reported to understand and get better overlay accuracy than tool
specification. It is needed to be verified that how much they take an effect on improving the DP overlay. Continuously
we can conclude that most efforts in DPT should be focused on overlay control issue.
ArF immersion lithography and RETs (Resolution Enhancement Technology) are the most promising technology for
sub 60nm patterning. As the device size shrinks, overlay accuracy has become more important due to small overlap
margin between layers. Overlay performance of immersion process is affected by thermal effect due to water evaporation,
so it shows worse performance than dry process and CD variation in DPT (Double Patterning Technology) process is
affected by overlay performance. So improvement of overlay accuracy became hot issue in realization of future
lithography technology, especially immersion process and double patterning process. Current status of lithography tool
shows 10 ~ 12nm (3sigma) overlay control in front-end process, but this overlay performance is not sufficient for
In this paper, we investigated the causes of overlay variation and tried to improve overlay accuracy in front-end process
of 60nm DRAM device. Therefore, the results in this study can be implemented to new technology such as immersion
and double patterning. First, overlay residual error factor is classified into two types, one is the equipment error factor
and the other is process error factor. Equipment error can be divided into SCMV (Single Chuck Mean Variation) by stage
accuracy variation, chuck to chuck mean and correction factor variation by using twin chuck etc. And process error can
be divided into alignment signal variation by chuck defocus (stage particle by contamination), increase of overlay
residual by material deposition, alignment key height variation by etch loading effect, overlay vernier attack by CMP
(Chemical Mechanical Polishing) process etc. We analyzed causes of these overlay error factor and we applied new
system and process to improve these overlay error factor.
In conclusion, we were able to find where overlay error comes from and how to improve overlay accuracy in 60nm
device, and we got good overlay performance using new alignment system and process optimization.
Though immersion lithography is on the verge of starting mass-production, demerit in overlay controllability by
immersion is thought as one of last huddle for that. The first issue in immersion tool has not been matured compared to
dry tool. As design rule is getting smaller, overlay specification is also changing the same way. But immersion tool is
not ready to meet this tighter overlay specification. The second issue is regarding the material which is used for
immersion process: top coat and water. Process details of material are needed to be verified thoroughly about how each
parameter affect on alignment and overlay respectively. In this paper, we made a split experiment about machine
parameter and investigated top coat effect on overlay. To improve overlay performance of immersion, we analyzed
machine parameters: scan-speed, settling time, UPW(Ultra Pure Water) flow etc. And we made an experiment about
how the effect of top coat is appeared on overlay through simulation and experiment. In the experiments, we used
ASML 1400i scanner. Resolution improvement of immersion tool has been proved by lots of papers, but it is need to be
verified of overlay controllability that getting tighter. Continuously, we believe that most efforts are to be focused on
overlay control issue.
Though speculation on immersion is ignited by the possibility in realization of hyper NA lithography system which will have NA> 1.0, it is thought that the immersion era might come earlier even in ≤1.0 NA regime because of great benefit in increasing DOF. On the other hand, questions are still laid on maturity or reliability issues such as lens contamination, bubble defects, overlay control and so forth. The main subject of this paper is how to find the appropriate time for introduction of immersion. Basic performance of immersion lithography in 80nm DRAM is compared with that of conventional dry lithography through experiment and simulation. Result of simulation is quite well matched with that of the experiment, and therefore we can investigate the limit of conventional dry lithography based on the simulation results.60nm node might be remained as a last regime for conventional dry lithography by virtue of polarized illumination, and we can expect the shoreline beyond there.
As design rule shrinks down continuously, various technology have been developed to extend the resolution limits of lithography. One of those is Double Exposure Technology(DET). This paper is about not only resolution improvement but also Critical Dimension(CD) variation reduction with DET. As the design rule shrinks below 100nm, the core/peripheral area where we used to think we had sufficient margin is becoming the bottle neck for device fabrication. In this paper, in order to compare optimized single exposure (cell focus) and DET (cell, core/peripheral focus) for critical dimension uniformity(CDU) on cell and core/peripheral area, CDU was measured from wafer by use of simulation and measurement. Gate layer of DRAM device was used for the experiment. Exposure condition for the single exposure was set to crosspole and for DET, dipole and conventional respectively. Optical proximity correction(OPC) was done with in-house simulation tool on stiching area of the double exposure experiment. Same exposure tool and same process condition were used for each experiment and only the exposure condition was changed to compare local CDU, intra-field CDU, wafer CDU to find out how much CD variation can be reduced.
The purpose of this paper is to do the direct comparison of between the novel chrome-less phase shift mask (CLM), which is suggest by Chen et. al. recently, and attenuated phase shift mask which has been in the main stream of DRAM lithography. Our study is focused on the question of whether the CLM technology has a potential advantages compared with attenuated PSM, so as to substitute the position of it in 0.3 k1 lithography era of DRAM. Firstly, some basic characteristics of both masks are studied, that is intensity distribution of diffraction orders and optical proximity effect etc. And then mask layouts are optimized through the resist patterning simulation for various critical layers of DRAM with CLM and attenuated PSM, respectively. Resolution performances such as exposure latitude and DOF margin and mask error enhancing factor etc. are compared through the simulations and experiments. In addition, it is also studied in the point of mask manufacturing of CLM such as phase control issues, defect printability, mask polarity, and so forth.
As ArF process will be substituted for KrF process at below 0.13 um node, it is time to study CD budget of mask error in ArF lithography. The purpose of this study is to investigate printability of ArF mask defects and corresponding effective specification in repeating cell. Mask defects in regularly repeated pattern were classified as point defect, line defect, and are defect, for convenience's sake, according to their sizes and lithographic explanations. Based on such classification, test reticle (ArF attenuated PSM) was manufactured in our captive mask shop. After exposed at a nominal dose and e-beam cured, each defects was inspected to extract effective specification for ArF process. MNPD (maximum non-printable defect) sizes of various duty patterns were manifested in point defect. In line defect and area defect, as the base pattern CD and duty ratio changed, the slope (MEF) of linear fitting was obtained. Maximum CD deviation from mean CD could be calculated from it. Mask CD budget was considered as 50% of total wafer CD error (10% of target) for mask spec generation. Experimental result was compared with DAIM (diffused aerial image model)-based simulation result because experiment had the error that arose from e-beam curing.
With smaller features sizes and higher pattern densities on high-end mask for DUV lithography, pattern fidelity on mask features becomes essential for optical proximity correction (OPC) performance. But some degree of corner rounding on the mask is inevitable even using the latest writing tool. The corner rounding radius on mask is mainly determined by the resolution of writing tool, mask resist process and chrome etching process following. In this paper, we will first discuss corner rounding impact for two-dimensional pattern applied OPC. Secondly modeling mask patterning process by applying diffused aerial image model (DAIM). Thirdly we will compare mask simulation results and mask SEM image for various mask masking process. Finally, we will examine a new simulation method to enhance the accuracy of wafer patterning simulation by using not CAD layout but mask layout extracted from mask patterning simulation.
Optical lithography makes various problems in the low k<SUB>1</SUB> range due to high MEF and low process margin. This has an impact upon CD variation, pattern collapse, pattern thinning, and undesirable repeating defect throughout the wafer process. Moreover, it is difficult to understand main factor that affected process problems. In this paper, mainly we study impacts on wafer process using 120nm design rule mask. Experimentally, w use full field mask composed of DRAM structure with cell array and periphery patterns. 0.70 NA KrF exposure tool and APSM are used to get high process margin and good pattern fidelity. As a result, we got about 10 percent EL and 0.5 micrometers DOF or more in actual process. Also CD variation was controlled within 15nm using CMP and BARC. However, mask CD variation was amplified on wafer, especially wafer CD variation was very serious in the edge of cell array by optical proximity effect, stand wave effect, and mask. Patterning and etching process occurred line thinning, and it was inspected as repeating defect. TO get optimum process result, it was very important to control mask CD and wafer CD within process window after mask CD correlation. We could find that mask or wafer process have an influence on unexpected problem for 120nm process with low k<SUB>1</SUB> value.