Proc. SPIE. 5376, Advances in Resist Technology and Processing XXI
KEYWORDS: Lithography, Optical lithography, Calibration, Interfaces, Electron microscopes, 3D modeling, Scanning electron microscopy, Thermal modeling, Resolution enhancement technologies, Temperature metrology
The PR(Photoresist) flow process after the development step has been used for patterning of sub-200nm contact holes as the design rule decreases rapidly. To optimize the layout design and process parameters, we develop the new viscous PR flow model which is verified for various PRs by experimental results. Using the model and simulation, we demonstrate the close agreement with VSEM(vertical scanning electron microscope) of the top corner rounding profile of PR and investigate the effect of the dominant variables such as the contact size, surrounding bulk density, and temperature. This model is also integrated with lithography simulator. The layout design and process condition of patterns with various contact sizes are optimized by using our new methodology. The viscous flow model linked to the lithography simulator can be effectively used in predicting the contact patterning process and optimizing the layout as well as analyzing defects.
As semiconductor devices are scaled down to the sub-100nm node, the fine control of ACLV (across-chip line-width variation) to improve the performance of chips and the expansion of the process window to enhance yield are required. One of the techniques reducing ACLV is MPPC (model-based process proximity correction). However, it increases pattern complexity and does not guarantee enough process windows. Therefore, we propose a HPPC (hybrid PPC) methodology combining RPPC (rule-based PPC) and MPPC, which correct the gate on active by MPPC for device performance and the field gate by RPPC for process window. In addition, we optimize SRAF (sub-resolution assist feature) design to improve process windows further at the full chip level and apply the multi-step correction, which corrects optical and etch proximity effects separately to minimize ACLV. As the result of the application to the 90nm logic gate, we achieve over 0.3um DOF (depth of focus) and the line-width variation within ±5% of the target CD (critical dimension).