For 1xnm node and beyond, even Extreme Ultraviolet Lithography (EUV) technology, the serious geometries distortions of the wafer patterns at new process are forcing chipmakers and foundries to utilize model-based SRAFs for ensuring the accuracy and manufacturability of the chips. Model-based Sub-Resolution Assistant Feature (SRAF) is based on inverse lithography (ILT), which is accurate but time-consuming. Therefore, it is necessary to extract the SRAF rules from model-based results and apply them to full chip layout. In this paper, we put forward a methodology of 2D SRAF rule extraction based on model-based results. We can describe and locate the SRAFs by introducing Projection Region, because it reflect the relationship between the SRAFs and main patterns. And the new concept Elongation can make the properties of SARFs more clearly. The experimental results show that the proposed method can extract the 2D SRAFs accurately and output the rules in a general format. The rule simplifying step can decrease the quantity of 2D SRAF rules through the identification and process of symmetry.
As the semiconductor industry enters 20 nm node and beyond, design restrictions and process complexity lay stress on the development for a new technology node. This paper introduces a hybrid hotspot library building method based on simultaneous optical and geometry analysis, which could help explore design rule optimization and enhance cycle time at early stage for new node development. Lithography simulation results verify the accuracy of this method. This method provide a feasible way to build up a preliminary Design Rule Checking (DRC) library even before process-freezing.
With the shrinking of critical dimension, the demand for a process window has reached a new level, which is denoted as the depth of focus at certain exposure latitudes. Therefore, high-quality monitoring and controlling of focus shift are becoming more and more critical. With the purpose of providing an optimal focus monitoring mark, which can be applied in freeform or off-axis illumination with a big sigma and hypernumerical aperture (NA) scheme, a global optimization method combined with the idea of a genetic algorithm is developed. For illustration, two optimal mask structures under quasar and freeform illumination conditions are given by the optimized method. The numerical simulations with the lithography simulator PROLITH are provided to demonstrate the performances of these two structures. In addition, the robustness of these optimized structures is analyzed by considering the phase-shift error in mask manufacturing. The above simulation results verify the effectiveness and validity of the proposed optimization methodology and also show that the mask structure provided by the optimized method has the potential to be an efficient candidate for measuring the defocus of scanners in the immersion lithography with hyper NA.
We demonstrate two different approaches of implementing design technology co-optimization (DTCO). One is on optimizing standard cells. Before being placed on mask, standard cells can be evaluated and optimized to gain better process windows. This approach enables an additional learning cycle before mask tapeout, reducing process development cost. The other approach uses a random pattern generator to create various patterns with high coverage based on given design rules. Lithography simulation is used to evaluate process window of these patterns, and annotates its printability. Test patterns generated in this way can be used for early process development.
This paper proposes a novel hotspots fixing flow, in which design rule optimization and lithography RET solution are obtained simultaneously. This flow is most effective in the early development phase, and its methodology is rooted from design technology co-optimization (DTCO). Two layout files, corresponding to separate colors of a double-pattern layer (10nm node M1), are first generated by a pattern generator, and they meet no-stitching requirements and are design rule check (DRC) clean. Then, source, mask and design rule co-optimization is done with the layouts, and the design rules are optimized to remove hotspots and enable maximum lithography process window (PW). The mask optimization (MO) in combination with cost function manipulation and design rule optimization improve the robustness of initial design rule. The application of the methodology illustrates a friendly design rule and avoids later design rework.
ASML AH53 and AH74 with higher odd-order diffraction light are the widely used alignment marks in industry to achieve better alignment accuracy by reducing mark damage noise. During lithography alignment process, decent diffraction light power is the basic demand. However, with the use of some high absorption (k is not equal to 0 for detective wavelength) material, it is difficult to detect the light power reflecting from the thick and opaque film stacks with these standard alignment marks. Here we optimized four alignment marks with higher odd-order diffraction power with comparing with AH53 and AH74. One software based on Fourier optical theory is built to quickly calculate the wafer quality (WQ) of different film stacks and different alignment marks. ASML SMASH alignment system can accept customized alignment mark, with new mark type configuration file. In order to demonstrate the effectiveness of new alignment marks, we put the marks on a mask and do the experiments to compare with simulation results. All the experiments results show that new designed alignment marks have larger WQs of odd-order diffraction.
As the fin based field effect transistors (Fin-FET) emerge, the device structure is changed from two dimensional to three dimensional. Due to the existence of topography, the lithographic performance may be affected and, in most cases, becomes more complicated, especially in the ion implantation process after gate being constructed. In this paper, the various parameters that may have influence on the resist topography are being investigated, such as the density, height, and corner rounding of the fin structures, the height, and the corner rounding of the gates, etc. Theoretical analysis shows that the resist image intensity among the fins and gates can be improved by increasing the thickness of the oxide on the edge of the gate. Following the above theoretical analysis, a method for lithographic performance improvement with the existence of resist topography is proposed. The method is demonstrated from the simulations with the lithography simulator PROLITH. With an optimal thickness of oxide on the surface of gate, the residual resist in the topography after development will be removed thoroughly. Compared with other methods, the proposed method requires neither a specific system setup nor an additional etch process, which is a tremendous cost-saving in mass production.
Typically, the printing of contact patterns uses a dark-field (DF) mask in combination with a positive tone resist and positive tone development (PTD) process. PTD, which has a mature process and simulation model, had been widely applied in high-volume manufacturing. For the low aerial image quality of a DF mask in advanced node, PTD is substituted by negative tone development (NTD), which uses a positive tone resist and bright-field mask. Due to the high cost and immature simulation model of NTD process, it is worthwhile to extend PTD to some critical patterns. With the purpose of improving the resist profile and process window (PW) of the contact pattern with a PTD process in advanced node, an optimization method combined with the idea of a genetic algorithm is put forward. For performance of the optimized resist under the conditions of best focus and best dose, an evaluation based on the through pitch square contact patterns with the critical dimension (CD) fixed at 50 nm has been provided. The generalization performance of the optimized resist is also analyzed by a systematic method, which contains the resist profile and PW simulation on the base of through CD and through pitch contact patterns. The above simulation results verify the effectiveness and validity of the proposed optimization method.
Design and technology co-optimization (DTCO) can satisfy the needs of the design, generate robust design rule, and avoid unfriendly patterns at the early stage of design to ensure a high level of manufacturability of the product by the technical capability of the present process. The DTCO methodology in this paper includes design rule translation, layout analysis, model validation, hotspots classification and design rule optimization mainly. The correlation of the DTCO and double patterning (DPT) can optimize the related design rule and generate friendlier layout which meets the requirement of the 14/10nm technology node. The experiment demonstrates the methodology of DPT-compliant DTCO which is applied to a metal1 layer from the 14/10nm node. The DTCO workflow proposed in our job is an efficient solution for optimizing the design rules for 14/10 nm tech node Metal1 layer. And the paper also discussed and did the verification about how to tune the design rule of the U-shape and L-shape structures in a DPT-aware metal layer.
A new focus monitor mask having novel grating structure is proposed to measure the focus variation of the scanner. The grating pattern composes of transparent line, opaque line, π-phase shift groove and π/2 -phase shift groove with their width ratio equivalent to 1:4:1:2. By using this structure, one of the first order and one of the second order of the diffraction spectrum are eliminated. Therefore, the lithography image is formed by the interference of the zeroth order and the left positive (or negative) 1st and 2nd orders, which is more sensitive to the subtle change of focus. The basic principle and characteristic of the proposed mask is described in this paper. Simulations with the lithography simulator PROLITH shows that the monitoring accuracy is improved more than 25%, compared with the conventional phase grating focus monitor (PGFM). The novel mask proposed in our job has potential to be an efficient candidate for measuring the defocus of scanner in the immersion lithography with hyper NA.
With the development of the lithography, the demand for critical dimension (CD) and CD uniformity (CDU) has reached a new level, which is harder and harder to achieve. There exists reflection at the interface between photo-resist and substrate during lithography exposure. This reflection has negative impact on CD and CDU control. It is possible to optimize the litho stack and film stack thickness on different lithography conditions. With the optimized stack, the total reflectivity for all incident angles at the interface can be controlled less than 0.5%, ideally 0.1%, which enhances process window (PW) most of the time. The theoretical results are verified by the experiment results from foundry, which helps the foundry achieve the mass production finally.
The impact of mask three dimensions (M3D) effect on lithography processes is getting more pronounced from 32 nm nodes<sup>1-2</sup>. In this paper, we report four research progresses on the M3Deffect. Firstly, the impacts of M3D effect on the best focus (BF) offset were studied with though pitch as test pattern. The M3D effect has negative impacts on the BF, generating the BF offset pattern by pattern. The BF offset strongly depends on MoSi film thickness (THK). However the impact of MoSi profile, or side wall angle (SWA) could be ignored. Secondly, M3D OPC is needed to mitigate the shift of dose and focus center. Thirdly, as long as enough shade, the thinner MoSi, the less BF shift, as electromagnetic field (EMF) effect makes space behave smaller, which leads to higher contrast but higher mask error enhancement factor(MEEF); So the trade-off between contrast and MEEF is needed. And MoSi THK 43.7 nm in production supposed to be the optimized value from this study. Finally, compared to attenuating phase shifting mask (att.PSM) mask, opaque MoSi on Glass (OMOG) mask is more robust in terms of MEEF, the normalized image logarithmic slope (NILS) etc., not obviously influenced by mask duty ratio.