As technology advances, escalating layout design complexity and chip size make defect inspection becomes more challenging than ever before. The YE (Yield Enhancement) engineers are seeking for an efficient strategy to ensure accuracy without suffering running time. A smart way is to set different resolutions for different pattern structures, for examples, logic pattern areas have a higher scan resolution while the dummy areas have a lower resolution, SRAM area may have another different resolution. This can significantly reduce the scan processing time meanwhile the accuracy does not suffer. Due to the limitation of the inspection equipment, the layout must be processed in order to output the Care Area marker in line with the requirement of the equipment, for instance, the marker shapes must be rectangle and the number of the rectangle shapes should be as small as possible. The challenge is how to select the different Care Areas by pattern structures, merge the areas efficiently and then partition them into pieces of rectangle shapes. This paper presents a solution based on Calibre DRC and Pattern Matching. Calibre equation-based DRC is a powerful layout processing engine and Calibre Pattern Matching’s automated visual capture capability enables designers to define these geometries as layout patterns and store them in libraries which can be re-used in multiple design layouts. Pattern Matching simplifies the description of very complex relationships between pattern shapes efficiently and accurately. Pattern matching’s true power is on display when it is integrated with normal DRC deck. In this application of defects inspection, we first run Calibre DRC to get rule based Care Area then use Calibre Pattern Matching’s automated pattern capture capability to capture Care Area shapes which need a higher scan resolution with a tune able pattern halo. In the pattern matching step, when the patterns are matched, a bounding box marker will be output to identify the high resolution area. The equation-based DRC and Pattern Matching effectively work together for different scan phases.
Proc. SPIE. 9781, Design-Process-Technology Co-optimization for Manufacturability X
KEYWORDS: Oxides, Polishing, Data modeling, Calibration, Copper, Manufacturing, 3D modeling, Design for manufacturing, Transistors, Process modeling, Process engineering, Chemical mechanical planarization, Back end of line, Front end of line
Chemical mechanical polishing (CMP) has been a critical enabling technology in shallow trench isolation (STI), which is used in current integrated circuit fabrication process to accomplish device isolation. Excessive dishing and erosion in STI CMP processes, however, create device yield concerns. This paper proposes characterization and modeling techniques to address a variety of concerns in STI CMP. In the past, majority of CMP publications have been addressed on interconnect layers in backend- of-line (BEOL) process. However, the number of CMP steps in front-end-of-line (FEOL) has been increasing in more advanced process techniques like 3D-FinFET and replacement metal gate, as a results incoming topography induced by FEOL CMP steps can no longer be ignored as the topography accumulates and stacks up across multiple CMP steps and eventually propagating to BEOL layers. In this paper, we first discuss how to characterize and model STI CMP process. Once STI CMP model is developed, it can be used for screening design and detect possible manufacturing weak spots. We also work with process engineering team to establish hotspot criteria in terms of oxide dishing and nitride loss.
As process technologies move from planar transistor to 3D transistor like FinFet and multi-gate, it is important to accurately predict topography in FEOL CMP processes. These incoming topographies when stacked up can have huge impact in BEOL copper processes, where copper pooling becomes catastrophic yield loss. A calibration methodology to characterize STI CMP step is developed as shown in Figure 1; moreover, this STI CMP model is validated from silicon data collected from product chips not used in calibration stage. Additionally, wafer experimental setup and metrology plan are instrumental to an accurate model with high predictive power.
After a model is generated, spec limits and threshold to establish hotspots criteria can be defined. Such definition requires working closely with foundry process engineering and integration team and reviewing past failure analysis (FA) to come up a reasonable metrics. Conventionally, a potential STI weak point can be found when nitride residues remains in the active region after nitride strip. Another source of STI hotspots occurs when nitride erosion is too much, and active region can suffer severe damage.
In order to resolve the causality dilemma of which comes first, accurate design rules or real designs, this paper presents a flow for exploration of the layout design space to early identify problematic patterns that will negatively affect the yield.
A new random layout generating method called Layout Schema Generator (LSG) is reported in this paper, this method generates realistic design-like layouts without any design rule violation. Lithography simulation is then used on the generated layout to discover the potentially problematic patterns (hotspots). These hotspot patterns are further explored by randomly inducing feature and context variations to these identified hotspots through a flow called Hotspot variation Flow (HSV). Simulation is then performed on these expanded set of layout clips to further identify more problematic patterns.
These patterns are then classified into design forbidden patterns that should be included in the design rule checker and legal patterns that need better handling in the RET recipes and processes.
Advanced process nodes introduce new variability effects due to increased density, new material, new device structures, and so forth. This creates more and stronger Layout Dependent effects (LDE), especially below 28nm. These effects such as WPE (Well Proximity Effect), PSE (Poly Spacing Effect) change the carrier mobility and threshold voltage and therefore make the device performances, such as Vth and Idsat, extremely layout dependent. In traditional flows, the impact of these changes can only be simulated after the block has been fully laid out, the design is LVS and DRC clean. It’s too late in the design cycle and it increases the number of post-layout iteration. We collaborated to develop a method on an advanced process to embed several LDE sources into a LDE kit. We integrated this LDE kit in custom analog design environment, for LDE analysis at early design stage. These features allow circuit and layout designers to detect the variations caused by LDE, and to fix the weak points caused by LDE. In this paper, we will present this method and how it accelerates design convergence of advanced node custom analog designs by detecting early-on LDE hotspots on partial or fully placed layout, reporting contribution of each LDE component to help identify the root cause of LDE variation, and even providing fixing guidelines on how to modify the layout and to reduce the LDE impact.