A single-photon avalanche diode (SPAD) device with P+-SEN junction, and a low concentration of N-type doping circular virtual guard-ring was presented in this paper. SEN layer of the proposed SPAD has high concentration of N-type doping, causing the SPAD low breakdown voltage (~14.26 V). What’s more, an efficient and narrow (about 2μm) guard-ring of the proposed SPAD not only can withstand considerably higher electric fields for preventing edge breakdown, but also offers a little increment in fill factor compared with existing SPADs due to its small area. In addition, some Silvaco TCAD simulations have been done and verify characteristics and performance of the design in this work.
The charge transfer efficiency improvement method is proposed by optimizing the electrical potential distribution along the transfer path from the PPD to the FD. In this work, we present a non-uniform doped transfer transistor channel, with the adjustments to the overlap length between the CPIA layer and the transfer gate, and the overlap length between the SEN layer and transfer gate. Theory analysis and TCAD simulation results show that the density of the residual charge reduces from 1e11 /<i>cm<sup>3</sup> </i>to 1e9 /<i>cm<sup>3</sup></i>, and the transfer time reduces from 500 <i>ns</i> to 143 <i>ns</i>, and the charge transfer efficiency is about 77<i> e<sup>-</sup></i>/<i>ns</i>. This optimizing design effectively improves the charge transfer efficiency of 4T pixel and the performance of 4T high speed CMOS image sensor.
A behavior mode for simulating single-photon avalanche diodes is presented. The model is developed using Verilog-A
description language. The derived model is able to describe the static, the dynamic behavior, the triggering, the
self-sustaining and the self-quenching processes, and it also correctly characterizes the reverse current-voltage curve.
Simulation results confirmed the validity of the proposed model.
In this paper, a new UV and blue-extended photodiode with an octagon-ring-shaped structure is proposed, which have
increased responsivity for the UV and blue light, high responsive speed with short rise and fall time and UV/blue
selectivity. TCAD simulation approach is used to analyze the structural characteristics and photoelectric characteristics
of this new photodiode. For the structural characteristics, doping profile, potential distribution and Electric field
distribution are analyzed simply. For the photoelectric characteristics, the influences caused by doping concentration of
n-well on dark current, avalanche breakdown voltage and transient response are discussed in detail. The finger distance
(D) between two adjacent P+ anodes, the width (W) of P+ anode and the ratio of D/W are analyzed, witch affects the
spectral response, DC characteristic and transient response obviously. The work of TCAD simulation in this paper is
conducive to extract model parameters and process parameters of this new photodiode, which will further be used for
numerical simulation to analyze its photoelectric characteristics, noise characteristics more accurately. This work is also
a significant and helpful guide for device design and chip fabrication.
We propose a fully digital programmable gain amplifier scheme that overcomes the clipped noise analog-to-digital converter (ADC) for complementary metal-oxide semiconductor (CMOS) image sensors. Adopting the new digital programmable gain amplifier (DPGA) scheme, it obtains low noise and low power usage, has a small size, and high robust gain characteristic. To reduce the clipping noise, one new current controling the reference voltage of a 9-bit flash ADC is brought about in this work. Using the fully digital amplification scheme with reduced clipping noise ADC solves almost all the problems of the conventional analog programmable gain amplifier (APGA) scheme, which has large noise, large power, and big chip size due to APGA, and two analog autozero loop (both clamping circuit loop and offset correction loop) circuits. Based on a 0.18-µm CMOS image sensor process, one product of video graphic array (VGA) format CMOS image sensor is fabricated. The silicon test shows a 68-dB dynamic range with the power consumption of 80 mW at 24 MHz and the total noise of about 2 mV (at 30 fps and 27 deg).