A write driver for PCM is designed to improve reliability and bit yield in the write operation, due to the distributions during the phase change process. And the PCM cell can be injected by current or voltage respectively. Meanwhile, owing to the possible variations of the SET process parameters, the designed circuit can generate either multiple stepdown current pulse or multiple step-down voltage pulse. The circuit is developed based on SMIC 130 nm CMOS standard technology. Compared to the traditional constant current pulse programming, the test results show that the proposed multiple step-down current generator for SET operation can improve the uniformity of resistance and bit yield.
This paper presents an optimized write driver used in Phase change memory (PCM). To pursue fast RESET/SET operation, the proper clock scheme is applied, with the maximum frequency at about 200MHz. The write driver uses current pulses at a fixed frequency to successfully write into memory cells. Compared with the traditional SET operation, the novel dual-pulse SET operation divides the program pulse into 2 periods: pre-programming period provides large energy to cross the threshold-switching fast, programming period quenches the phase change resistance to that of the crystalline state. The optimization of the write operation decrease the program time and improves the resistance distribution.
A serial peripheral interface (SPI) 16-Kbit phase change memory chip based on 0.13μm CMOS process is designed. It contains a parallel error correcting code (ECC) circuit, which can correct 2 bits in every 8 bits without clock delay, enabling the write and read operations performed at bus speed. All the data transfers in 8-bit groups and can be read or written with write protection scheme by unlimited cycle, in which address can automatically increase one by one. Simulation results show that the chip can work correctly in SPI mode and with ECC scheme. It is now under testing.
An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.
Circuit design of an adaptable pulse current source chip is presented in this paper. The pulse current source is supposed to be used to supply Reset and Set current in the phase change memory chip testing system. The value and width of the pulse current source are variable, with the maximum value of 10mA and minimum width of 50ns. Two pulse currents output simultaneously with the same width but different values. A voltage pulse input is used to control the width of pulse current output. This high frequency voltage pulse could induce noise jamming to the inner circuits. To avoid this, a novel ESD and bonding structure is proposed.