A front-end design of an ASIC that implements calibration and correction for IRFPA non-uniformity is presented. An
algorithm suitable for ASIC implementation is introduced, and one kind of architecture that implements this algorithm
has been designed. We map the architecture to TSMC 0.25um process. After evaluating the chip area and operation
speed, we confirm that this architect will also be effective when the FPA scale in enlarged to 1Kby1K. Finally the flow of
circuit implementation and method of verification are introduced briefly.