A improved SPIHT image compression algorithm called symbol-map zero-tree coding algorithm (SMZTC) is proposed
in this paper based on wavelet transform. The SPIHT algorithm is a high efficiency wavelet coefficients coding method
and have good image compressing effect, but it has more complexity and need too much memory. The algorithm
presented in this paper utilizes two small symbol-maps Mark and FC to store the status of coefficients and zero tree sets
during coding procedure so as to reduce the memory requirement. By this strategy, the memory cost is reduced distinctly
as well as the scanning speed of coefficients is improved. Those comparison experiments for 512 by 512 images are done
with some other zerotree coding algorithms, such as SPIHT, NLS method. During the experiments, the biorthogonal 9/7
lifting wavelet transform is used to image transform. The results of coding experiments show that this algorithm speed of
codec is improved significantly, and compression-ratio is almost uniformed with SPIHT algorithm.
We present a scheme of integrated optical 3-D digital imaging (IO3DI) based on digital signal processor (DSP), which
can acquire range images independently without PC support. This scheme is based on a parallel hardware structure with
aid of DSP and field programmable gate array (FPGA) to realize 3-D imaging. In this integrated scheme of 3-D imaging,
the phase measurement profilometry is adopted. To realize the pipeline processing of the fringe projection, image
acquisition and fringe pattern analysis, we present a multi-threads application program that is developed under the
environment of DSP/BIOS RTOS (real-time operating system). Since RTOS provides a preemptive kernel and powerful
configuration tool, with which we are able to achieve a real-time scheduling and synchronization. To accelerate
automatic fringe analysis and phase unwrapping, we make use of the technique of software optimization. The proposed
scheme can reach a performance of 39.5 f/s (frames per second), so it may well fit into real-time fringe-pattern analysis
and can implement fast 3-D imaging. Experiment results are also presented to show the validity of proposed scheme.
An embedded three-dimensional (3-D) digital imaging scheme with a parallel fixed-point digital signal processor (DSP) is presented, which is based on temporal phase unwrapping and DLP digital projection technique. This scheme utilizes an embedded hardware structure with aid of parallel DSP to realize a pipeline procedure of the automatic analysis of fringe patterns, fringe patterns generation, fringe projection, and data acquisition. The software pipeline is also adopted in the procedure phase demodulation and phase unwrapping. The time of phase reconstruction with five-step phase shift is 0.89s for 262144 coordinates, and the fringe image processing speed is up to 39.5 f/s (frames per second), so it can meet the need of video-rate fringe images processing. Experiment results show that this embedded DSP imaging system is fast, reliable, low power cost, and it will be suitable for a wide range of practical measurement application.